Example MPC5746R PIT ISR GHS614

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********************************************************************************
* File:             main.c
* Owner:            b21190(Vlna Peter)
* Version:          1.6
* Date:             Oct-10-2017
* Classification:   General Business Information
* Brief:            Example contains startup with PLL0 200MHz as system clock
*                   and demonstrates PIT interrupt triggering.
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* Test HW:  MPC57xx EVB + MPC5746R minimodule
* Maskset:  1N83M (cut 2.0B)
* Target :  internal_FLASH
* Fsys:     200MHz PLL0 as system clock
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Revision History:
1.0     Oct-19-2015   b21190(Vlna Peter)  Initial Version
1.1    Nov-11-2015     b21190(Vlna Peter)  Added PPL0 200MHz as system clock
1.2    Dec-02-2015    b21190(Vlna Peter)  Added Flash controller init
1.3    Dec-02-2015    b21190(Vlna Peter)  Fixed system clock init
1.4    Feb-07-2017    b21190(Vlna Peter)  SWT0 and SWT1 disabled in startup
1.5     May-31-2017    b21190(Vlna Peter)  Fixed comments in AC6 (CLKOUT)
1.6     Oct-10-2017    b21190(Vlna Peter)  Added PIT + Interrupts
*******************************************************************************/

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