S12Z - Simulating ECC errors at RAM by debug access

Document created by Radek Sestak Employee on May 11, 2017Last modified by Radek Sestak Employee on Jan 16, 2020
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For debug purposes, it is possible to read and write the user data and

the ECC value directly from/to the SRAM memory. For these debug accesses a register

interface is available.


By the debug access and writing incorrect data + ECC values into the system memory, 

the single and double bit ECC errors may be simulated for checking the software error handling.


The debug registers may be modified only in a special mode.


The tested address 0x3000 is excluded from linker use - see prm linker file.


I hope it helps you.


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