Watchdog Timer

Document created by GUO XIAOLI Employee on Jul 13, 2012Last modified by johnmc on Dec 9, 2013
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Most embedded systems must operate continuously without any user input, even if something goes wrong. Most of us have

experienced having our desktop or laptop computer locking up and requiring a reboot of the system to get it working again. We simply

cannot afford to do this in an embedded system. Ideally, we would write our software so that it never crashes or fails. This, as you can

guess, is really hard to do and so our microcontroller manufacturer has included a hardware feature called the Computer Operating

Properly, or COP, reset generator. If this hardware feature does not receive a confirmation signal that our program is running properly,

it will generate a reset to restart our program from the beginning or from a restart place that we can choose. The COP is also called a

watchdog timer. 

 

The COP reset circuitry guards against our program not working properly by expecting the program to execute a particular sequence of
instructions at some interval. If the COP does not receive this sequence before it times out, it generates a reset by pulling the RESET_L
signal low. This can reset all peripherals connected to the reset line. The CPU then fetches a COP reset vector to restart the program
again. Thus the COP is treated like other interrupts except that it cannot be masked once the COP timer has been started. Often you
would like to restart at the beginning of your program but in some situations you may choose to enter some diagnostic routine, such as
updating a counter that counts the number of COP restarts that have occurred or lighting an LED, before restarting the program. You
may also wish to leave some debugging breadcrumbs to help you understand why the COP is resetting the program.

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