GPT Timer interrupt problem with MCF52235

[neumdx]

I just want to use the GPT gerenal timer function,but it didn't come into Gpt_IsrHandler. I referenced the 52235_RM,I think it must be the registers are not setting correctly,but didn't find the problem.

/* * File:  main.c * Purpose:       sample program * */#include "support_common.h" /* include peripheral declarations and more */#include <stdio.h>/******************************************************************** * MCF5xxx ASM utility functions ********************************************************************/asm void asm_set_ipl(unsigned long) {  link    A6,#-8    movem.l D6-D7,(SP)    move.w  SR,D7        /* current sr    */    move.l  D7,D0        /* prepare return value  */    andi.l  #0x0700,D0   /* mask out IPL  */    lsr.l   #8,D0        /* IPL   */    move.l  8(A6),D6     /* get argument  */    andi.l  #0x07,D6        /* least significant three bits  */    lsl.l   #8,D6        /* move over to make mask    */    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */    or.l    D6,D7           /* place new IPL in sr   */    move.w  D7,SR    movem.l (SP),D6-D7    lea     8(SP),SP    unlk    A6    rts }/********************************************************************/voidmcf5xxx_irq_enable (void){    asm_set_ipl(0);}/********************************************************************//* * Write new interrupt vector handler into the vector table * Return previous handler address **********************************************************/ uint32 mcf5xxx_set_handler (int vector, uint32 new_handler){    extern uint32 __VECTOR_RAM[];    uint32 old_handler;        old_handler = (uint32) __VECTOR_RAM[vector];    __VECTOR_RAM[vector] = (uint32)new_handler;    return old_handler;}/***********************************************************************************/__declspec(interrupt)void Gpt_IsrHandler(void){     MCF_GPTA_GPTFLG2 |= MCF_GPTA_GPTFLG2_TOF; // clear interrupt flag of channel 0    MCF_GPIO_PORTLD = 0x00;//light the LEDs}/***********************************************************************************/void GPT_Timer(void){          // open global Timer channel 0 interrupt of GPT      MCF_INTC0_IMRH &= ~(1 | MCF_INTC_IMRH_INT_MASK41);     // Specifies the interrupt level (1~7) and the priority within the level(0~7) for Timer channel 0 interrupt      MCF_INTC0_ICR44 = MCF_INTC_ICR_IL(3) | MCF_INTC_ICR_IP(6);         MCF_GPTA_GPTSCR2=(1                     |MCF_GPTA_GPTSCR2_TOI     //timer overflow interrupt enable                     |MCF_GPTA_GPTSCR2_PR_64); //65536/((60M/2)/64)=0.14s        MCF_GPTA_GPTPACTL = (1| MCF_GPTA_GPTPACTL_CLK_GPTPR);// Select the GPT counter input clock         MCF_GPTA_GPTFLG2 = MCF_GPTA_GPTFLG2_TOF; // clear flag of timer    MCF_GPTA_GPTSCR1 = MCF_GPTA_GPTSCR1_GPTEN;   // enable GPT }/**************************************************************************/int main(void){    mcf5xxx_irq_enable();   // setup interrupt handler of Timer Channel 0 of GPT     mcf5xxx_set_handler(64 + 41, (uint32)Gpt_IsrHandler);    GPT_Timer();    //LD port connect LED，set as GPIO function，output     MCF_GPIO_PLDPAR = 0x00;    MCF_GPIO_DDRLD = 0xff;         while(1)    {                   }     }

Message Edited by neumdx on 2009-06-03 03:22 AM

[SimonMarsden_de]

Hi

One suggestion. I notice that you have:

MCF_INTC0_IMRH &= ~(1 | MCF_INTC_IMRH_INT_MASK41);

MCF_INTC0_ICR44 = MCF_INTC_ICR_IL(3) | MCF_INTC_ICR_IP(6);

The two values 41 and 44 are not consistent. Are you unmasking the wrong interrupt in the first line?

Hope this helps.

Simon

[neumdx]

Thank you very much ! That's the problem.I have found the problem this afternoon.I'm too careless.

[LiKe]

Dear All

I try this code and I change to

MCF_INTC0_ICR41 = MCF_INTC_ICR_IL(3) | MCF_INTC_ICR_IP(6);

and test it.It is not 0.14s.is 0.28s why?

I debug it and I check MCF_GPTA_GPTFLG2 ,one time can clear,second time can not clear,thirth time can clear,fourth

time can not clear......why?

I use cw6.4.How to reader cpu vector base register CPU@ 0x 0800 etc?

by the way ,how to debug and check D6,D7,SR.....

asm void asm_set_ipl(unsigned long) {
    link    A6,#-8
    movem.l D6-D7,(SP)

    move.w  SR,D7           /* current sr    */

    move.l  D7,D0           /* prepare return value  */
    andi.l  #0x0700,D0      /* mask out IPL  */
    lsr.l   #8,D0           /* IPL   */

    move.l  8(A6),D6        /* get argument  */
    andi.l  #0x07,D6        /* least significant three bits  */
    lsl.l   #8,D6           /* move over to make mask    */

    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
    or.l    D6,D7           /* place new IPL in sr   */
    move.w  D7,SR

    movem.l (SP),D6-D7
    lea     8(SP),SP
    unlk    A6
    rts    
}