关于I.MX6Q的MIPI D-PHY clock的问题

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关于I.MX6Q的MIPI D-PHY clock的问题

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Simon_Wu
Contributor II

抱歉我的英语不好,因此使用中文。

 

我使用的摄像头是

lanes = 2-lanes mipi

width = 1104,

height = 1312,

fps = 75,

pixel format : RAW 10

根据AN5305,https://www.nxp.com.cn/docs/en/application-note/AN5305.pdf

Pixel clock = 1104 * 1312 * 75 fps * 1 cycle/pixel * 1.35 blank interval = 146.66 MHz

Total MIPI data rate is 146.66 MHz * 16 = 2346 Mb/s

MIPI clock = 2346 /2 /2 = 586.5 Mhz

MIPI_CSI2_PHY_TST_CTRL1 setting = 586.5 MHz * 2 (DDR mode) = 1173 MHz

但是i.MX6Q最高似乎只支持1000MHz,但我还是设置为0x74(950–1000 MHz)

接收数据得到的反馈是:ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

请问是i.MX6Q的D-PHY clock达不到要求,还是其他的问题?

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