make all SEMC accesses non-cacheable

[nickwallis]

Hi,

We have an FPGA that is connected to the SEMC interface. We are using the SEMC in PSRAM mode, ADMUX mode, ASYNC mode.

We want to make sure that all accesses to the FPGA result in a real hardware read/write transaction and do not use the cache.

How do I make sure of this, i.e. disable the cache for this region?

thanks!

[nickwallis]

thanks @gusarambula 

I only want to disable the cache for SEMC accesses, that looks like a global enable/disable? How do I disable the cache only for SEMC accesses?

What do these lines in board.c do?

    /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);

thanks!

[gusarambula]

Hello Nickwallis,

Those lines in the board.c make use of the CMSIS to define the memory regions and the MPU (Memory Protection Unit) settings, which divides the memory map into a number of regions and defines location, size access, and among other attributes if the region will be cacheable or not.

You may set the SEMC memory region as non-cacheable. The Region you shared would be the SEMC0 region. You may find some more details on how these regions are set in AN12042 (link below).

https://www.nxp.com/docs/en/application-note/AN12042.pdf

For more details on the MPU settings you may see the ARM Cortex-M7 documentation and also the mpu_armv7.h header where the CMSIS MPU functions are described.

I hope that this information helps!

Regards,

Gustavo

[nickwallis]

Thanks for the reply.

My question remains - how do I disable the cache for all SEMC accesses? This is using mcuxpresso IDE.

[gusarambula]

Hello nickwallis,

My apologies.

The DCACHE and ICACHE are enabled by default on the board.c file. You may disable them with the SCB_DisableDCache() and SCB_DisableICache() functions that are part of the CMSIS libraries.

I hope that this information helps.

Regards,
Gustavo

[gusarambula]

Hello nickwallis,

Yes, disabling the cache would allow you to ensure that each read/write are real transactions. However, while it would ensure actual access to the hardware, it will be detrimental to the performance. You may find some numbers in AN12437.

https://www.nxp.com/docs/en/application-note/AN12437.pdf

https://www.nxp.com/docs/en/application-note-software/AN12437SW.zip

I hope that this information helps!

Regards,
Gustavo