Using the AOI module to perform logical operations on the digital inputs.

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Using the AOI module to perform logical operations on the digital inputs.

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oayastuy
Contributor II

Hello everyone,

I would like to perform the logical AND operation on two digital inputs and route it to the FAULT signal of the PWM by hardware using the i.MXRT1170. In other words, I want the pwm1Fault0 signal to be LOW when both digital inputs are HIGH.

Analyzing the reference manual in the section "Chapter 81 On Chip Cross Triggers Overview," I came across the following diagram:

oayastuy_0-1684836939038.png

Upon analyzing the diagram, it appears that the following flow is possible:

IO PAD --> XBAR2/XBAR3 --> AOI --> XBAR1 --> FlexPWM

To my surprise, when examining the section "4.6 XBAR Resource Assignments," IO PAD is not listed as a possible input for XBAR2 and XBAR3. However, it is available for XBAR1. Unfortunately, XBAR1 does not allow me to perform the AND operation on the signals.

Therefore, I have the following questions:

  1. Why does the diagram show IO PAD as an input for XBAR2 and XBAR3, but it is not listed in the resource assignments?

  2. Is it possible to achieve what I need? If so, how can it be done?

  3. If it is not possible, is the diagram incorrect?

Thank you for your help.

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_Leo_
NXP TechSupport
NXP TechSupport

Sorry for the inconvenience, I thought you were checking this issue with your distributor, who referenced this community post.

The IO PADs are not routed to XBAR2 and XBAR3. There appears to be an error in Figure 81-1. On-Chip Cross Trigger Network.

The best reference I can give you is the SDK example evkmimxrt1064_pwm_fault, which sets the PWM Fault inputs to CMP0 output pin through XBAR1.

You could try the signal routing you mentioned but instead of using IO PADs, use ACMPs.

Hope it helps you.

Have a nice day!

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3 Replies
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_Leo_
NXP TechSupport
NXP TechSupport

Thank you so much for your interest in our products and for using our community.

I noticed that you have another similar case, so I will follow up on this last one that I mention.

Have a nice day!

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oayastuy
Contributor II

Hello,

What is the similar case you are referring to?

Thanks in advance,

Odei

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_Leo_
NXP TechSupport
NXP TechSupport

Sorry for the inconvenience, I thought you were checking this issue with your distributor, who referenced this community post.

The IO PADs are not routed to XBAR2 and XBAR3. There appears to be an error in Figure 81-1. On-Chip Cross Trigger Network.

The best reference I can give you is the SDK example evkmimxrt1064_pwm_fault, which sets the PWM Fault inputs to CMP0 output pin through XBAR1.

You could try the signal routing you mentioned but instead of using IO PADs, use ACMPs.

Hope it helps you.

Have a nice day!