RT1176: Unexpected USB endpoint side effects

[udoeb]

Hello,

We use the following endpoint setup:

Endpoint 0x83 (IN)
Transfer type: Interrupt
wMaxPacketSize = 0x06 (6 bytes)
bInterval = 4 (8 microframes)

Endpoint 0x03 (OUT)
Transfer type: Isochronous
wMaxPacketSize = 0x0A3C (2 x 572 bytes multi-packet transfer)
bInterval = 1 (1 microframe)

The scenario is as follows:
The device is running at high speed, EP 0x83 is enabled and the host is periodically sending IN tokens. EP 0x83 has no data and replies with NAK to each IN token. Then we enable EP 0x03 but there is bus activity for this endpoint yet. Now we observe that there are unexpected TD completions on EP 0x03.
These completions happen at an interval of 8 microframes which makes us believe that this is a side effect of the IN or NAK packet on EP 0x83. In each completed TD the Transaction Error bit in the Status field is set.

There should not be any TD completions for an endpoint when there is no bus activity for that endpoint. This causes unncessary interrupts and wasts CPU cycles.

We think this is a silicon issue. Possibly it is related to ERR050101 that has been documented for RT1050 series.

Note: The issue does not occur if the endpoint address does not overlap, e.g. if EP 0x84 and EP 0x03 is used.

[RaRo]

Hello @udoeb,

Could you please tell us which board are you using? Is an NXP's EVK or is a custom one?

Looking at the i.MX RT1170 Processor Reference Manual. Chapter 62. Universal Serial Bus Controller (USB) mentions the following about wMaxPacketSize:

[i.MX RT1170 Processor Reference Manual. Chapter 62. Universal Serial Bus Controller (USB). Table 62-12. iTD Buffer Pointer Page 1 (Plus)]

As Endpoint 0x03 (OUT) uses a wMaxPacketSize greater than 0x0400, it could explain the erroneous behavior.

Best regards, Raul.

[udoeb]

Hello Raul,

This is a custom hardware. I don't think this makes a difference as the issue is related to the USB IP in the SoC entirely.

We set a wPacketSize of 572 bytes but use 2 transfers per microframe using the High-Bandwidth Pipe Multiplier (Mult) bits in the endpoints Queue Head. See Table 62-30 in the manual.

For details on multi-packet isoch transfers, see also USB 2.0 spec.

Regards,
Udo