RT1052 Hyperflash simulation at 333MHz DDR

[DanRumary]

Hello

I am having trouble simulating the Hyperflash running at 333MHZ DDR (166MHz clock) on my design, the eye diagram basically falls apart when simulating randomised data. When I run at 266MHz DDR (133MHz clock) the eye diagram is nice and clean.

I have setup simulated scenarios even with the perfect 50 Ohm trace from 1mm to 50mm in length and I get the same results proving its not related to my layout. I have tried swapping out the IBIS model with the Hyperflash model for the DQ pins and this gives me a nice clean eye diagram which leads me to believe that the RT1052 processor IBIS model may either be incorrect or that the processor does not support 333MHz DDR Hyperflash .

The only IBIS model I could find is rt1050_bga12x12_0.8pitch where we are using the 10x10mm 0.65mm pitch BGA

[DanRumary]

Thank you for your reply Jay.

Yes I saw that too in the datasheet but as I`m simulating the output pins using the IBIS models NXP provided those registers are irrelevant.

I do have options of drive strength and slew rate but even at the strongest settings the simulation suggests its not possible.

Dan. 

[jay_heng]

From RT1050 data sheet, FlexSPI can support up to 166MHz DDR. for some dedicated memory model, you may need to adjust FlexSPI->DLLACR/DLLBCR for timing.