RT1052: Can CSI VSYNC be set to falling-edge triggered?

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

RT1052: Can CSI VSYNC be set to falling-edge triggered?

345件の閲覧回数
udoeb
Contributor II

Hello,

The manual states in section 34.3.1.2 Gated Clock Mode:

The CSI can be programmed to support rising/falling-edge
triggered VSYNC through CSI_CR1[SOF_POL]

However, when I set SOF_POL=1 this has no effect. CSI still triggers on rising edge.

I'm using traditional interface, CCIR_EN=0, CCIR_MODE=0, EXT_VSYNC=0.

Question: How can VSYNC be configured for falling edge?

Thanks
Udo

0 件の賞賛
3 返答(返信)

322件の閲覧回数
jingpan
NXP TechSupport
NXP TechSupport

Hi @udoeb ,

This is a interrupt control bit. Can you share how to test this condition?

 

Regards,

Jing

0 件の賞賛

306件の閲覧回数
udoeb
Contributor II

Hi,

Thanks for your reply.

Let me rephrase the question: I do apply an external signal to VSYNC and notice that the DMA starts on the rising edge. My external circuitry requires that DMA starts on the falling edge. How can I achieve that?

Regards,
Udo

0 件の賞賛

301件の閲覧回数
jingpan
NXP TechSupport
NXP TechSupport

Hi,

But SOF_POL default is 0, it is falling edge. SOF_POL=1 means rising edge. Opposite to your setting. So...

 

Regards,

Jing

0 件の賞賛