MX RT 1021 - How to use SDRAM in low power mode

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MX RT 1021 - How to use SDRAM in low power mode

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tbtbtbt
Contributor III

I am using SDRAM for global data placement in my program. It is necessary to use SDRAM for my application. I have implemented powermode switch driver based on the SDK example, and all works well. The SDRAM is initialized through default dcd.c by defining "XIP_BOOT_HEADER_DCD_ENABLE" and "SKIP_SYSCLK_INIT" in the preprocessor. Similarly, SDRAM works well on its own. 

When entering low power mode, the code hardfaults with an instruction bus error. I understand that this is because in low power mode the system PLL, which the SDRAM uses as it's clock source, is disabled. I am wondering if there is a way to switch the SDRAM clock source to the external oscillator so it can remain active in low power mode. Reading through other forum posts, it sounds like it is a very bad idea to mess with the SEMC clock source.

So I'm wondering what the best way to handle this is. I must use the SDRAM, since we are using files that take up too much memory to be placed in the on-chip RAM, but I'm not sure how to ensure SDRAM stays active during low power mode without modifying its clock.

I read about enabling self-refresh mode for the SDRAM before entering low power mode, and I tried to implement this in my project, but I don't think that the SDRAM is accessible in low power modes with this method, it just ensures that the data within the SDRAM isn't lost. So I don't think that this can be a solution.

What would be the best way to use SDRAM in low power mode and with the power mode switch driver?

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jingpan
NXP TechSupport
NXP TechSupport

Hi @tbtbtbt ,

In low power run mode, SEMC clock can't stay at a high clock rate because system PLL and other PLL are powered down. You can set SEMC clock to 24M for maximum. Before change the clock, you can let SDRAM run at self-refresh mode. Then change the clock and SEMC settings. After that, SDRAM should be able to read/write again. There is no rule says SDRAM can't run at 24M. Take W9812 as example, the maximum CLK Cycle Time is 1000ns.

 

Regards,

Jing

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