MIMXRT685-EVK: I3C Slave Reset pattern

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MIMXRT685-EVK: I3C Slave Reset pattern

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franco_brucato
Contributor I

Hello,

I'm using this board as I3C master. I'm trying to send an IBHR (Slave Reset) pattern, but unfortunately I'm not able to.

In the RT6xx user manual, the MCTRL register's description says:

REQUEST = 6 => FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it does a forced reset (will always reset).

TYPE = 0 => I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern.

TYPE = 3 => For ForcedExit, this is forced IBHR.

so, to my understanding, the following code should generate an IBHR pattern: I3C->MCTRL = I3C_MCTRL_REQUEST(6) | I3C_MCTRL_TYPE(3);

However, with this code I get just the HDR Exit pattern, that should be generated with I3C->MCTRL = I3C_MCTRL_REQUEST(6) | I3C_MCTRL_TYPE(0);

Am I doing something wrong or is the Slave Reset pattern not supported?

Thanks!

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Franco_brucato,

Allow me to inquiry internally is there are known issues. Given the documentation and the register definitions on the SDK your understanding is correct so it’s odd that the IBHR patter is not being generated.

I will let you know as soon as I have more information.

Regards,
Gustavo

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franco_brucato
Contributor I

Hi Gustavo,

thanks for your answer.

Do you have any update on this?

 

Regards,

Franco

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128 Views
gusarambula
NXP TechSupport
NXP TechSupport

Hello Franco_brucato,

I am still waiting for more information on this matter. My apologies. Rest assured that I will update this thread as soon as I have an update.

Regards,

Gustavo

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Franco_brucato,

My apologies for the delay.

I confirmed that this seems to be odd behavior.

Would it be possible to know more details about the leader/master and follower/slave configuration? Presumably the i.MXRT685 is the leader/master, but what device is working as the follower/slave?

If you could also share a waveform illustrating the I3C the leader/master is generating? If you do not which to share this information on the public communities you may open a service case to share them privately.

I will be looking forward to hearing back from you.

Regards,
Gustavo

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franco_brucato
Contributor I

Hello Gustavo,

thanks for the answer.

As you said, MXRT685 is the master, while the slave is an I3C device that is still not in production. Anyways, for this particular case, the slave is not relevant since the IBHR is a sequence completely driven by the master. The slave will just monitor that the IBHR pattern is received and then reset itself depending on the RSTACT configuration. So, the IBHR pattern should be generated on the bus even if no slave is connected to the bus.

I attach the waveforms I get when I try to perform just the IBHR pattern on a bus without slaves: it's just the HDR Exit Pattern, i.e. a shorter version of the IBHR pattern. However the result doesn't change when I connect my slave and perform other I3C operations before trying to send the IBHR pattern.

I attach also the code I'm using to configure the master and send the IBHR pattern. I'm using SDK version 2.10.1

Thanks!

 

 

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Franco_brucato,

Thank you for the additional details! Allow me to check with our experts and I will let you know as soon as I have more information.

Regards,
Gustavo

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