IMXRT1024 LPUART eDMA bytesEachRequest Parameter Manipulation

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IMXRT1024 LPUART eDMA bytesEachRequest Parameter Manipulation

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Lukas_Frank
Contributor IV

Hi all,

I wonder how many bytes are received between two ISR in LPUART? So, I can be widened my question with these two examples:


Ex1(With eDMA);

For example, we will be receiving 64 byte with LPUART1 to our buffer. What is the size of transferred data between two IRQ request during receive operation? I just tried to observe in the code this scenario but I did not.  Byte the way I mention about hardware interrupt.

Is that working like these:

  • take 4 word and one IRQ is occured,
  • then take one more 4 word after that one more IRQ is occurred,
  • then it goes like above until the end of 64 byte.
  • Finally 16 IRQ is occurred until the end of 64 byte transmission. 

Do we able to change bytesEachRequest parameter for EDMA_PrepareTransfer method? It is setted sizeof(uint8_t) as default in SDK.

 

Ex2(Without eDMA(LPUART Interrupt Based Method));

We have 4 word as maximum number of RXFIFOSIZE in LPUART according to Reference Manual. Correct me if I am wrong. When we start to data transfer for receive operation for 64byte. How it is going on at the hardware side?

Is that working like these:

  • take 4 word and one IRQ is occured,
  • then take one more 4 word after that one more IRQ is occurred,
  • then it goes like above until the end of 64 byte.
  • Finally 16 IRQ is occurred until the end of 64 byte transmission. 

Thanks and Regards.

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1 Solution
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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Lukas_Frank ,

  Your suspect is reasonable.Sorry for my misleading.

  I double check the RT1024 register, you are right, the RT1024 FIFO depth is fixed to 4 datawords, just like the readout situation. and the PARAM register also indicate:

kerryzhou_0-1632970060233.png

So, the FIFO size for more than 4, can't be set.

 So, when you do the transfer more than 4 words, you still need to do software counter, hardware can't set it directly.

Best Regards,

Kerry

 

 

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6 Replies
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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Lukas_Frank 

  I wonder how many bytes are received between two ISR in LPUART? 

Answer: the received ISR is determined by your LPUART, so you can define each receive interrupt length.

1. with DMA

  You can use the  receiveXfer.dataSize = ECHO_BUFFER_LENGTH; define the received datasize.

Your mentioned interrupt should be the DMA transfer finished interrupt, not the UART interrupt, as the UART related receive status will trigger the DMA transfer, then you can set the DMA desired received length to trigger the interrupt.

2. without DMA, use interrupt

Then you can set your receive FIFO Buffer depth.

kerryzhou_0-1632473309101.png

Then use the related interrupt(eg, overrun interrupt) to trigger your designed interrupt. As the FIFOSIZE will set the FIFIO buffer depth, then the received data will be saved to the FIFO, when it is overrun, then it will trigger the interrupt, you will know your FIFO buffer is full.

 

Best Regards,

Kerry

 

 

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Lukas_Frank
Contributor IV

Hi Dear @kerryzhou , 

 

Thanks for your reply. I have two more question to be sure about the FIFO size in interrupt mode. It is important for me because I will use either DMA or Interrupt in my case.

 

Q1:

What is the maximum number that it can be set RXFIFOSIZE from driver level or anything? I ask this question because RXFIFOSIZE field stated as read-only in RM. I tried to set it in the driver side, but after I set it as 256 word I see it is failed when I check the register values in debug mode. 

Lukas_Frank_0-1632646447647.png

Q2:

Is RXFIFOSIZE assignment process is platform-dependent issue? Does it vary between model of used processor? So, Is not it possible at all to set FIFOSIZE to 256 words?

 

Thanks and Regards.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Lukas_Frank 

   Good question!

  Please enable the FIFO at first, eg, TXFE=1, RXFE=1, then try to modify the FIFOSIZE again

kerryzhou_0-1632718285622.png

if you still have issues, please kindly let me know.

If the FIFO is not enabled, the FIFOSIZE is the 1 dataword in default.

Best Regards,

kerry

 

 

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Lukas_Frank
Contributor IV

Hi Dear @kerryzhou ,

 

I tried it before the push my question. After your feedback I tried it again. FIFO enabling and disabling working fine but size assignment is not successfully completed.

Do you share me if it is possible or not? According to RM and test result it is not possible to set FIFO size of LPUART as 64,128,256 etc.

Thanks and Regards.

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56 Views
kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Lukas_Frank ,

  Your suspect is reasonable.Sorry for my misleading.

  I double check the RT1024 register, you are right, the RT1024 FIFO depth is fixed to 4 datawords, just like the readout situation. and the PARAM register also indicate:

kerryzhou_0-1632970060233.png

So, the FIFO size for more than 4, can't be set.

 So, when you do the transfer more than 4 words, you still need to do software counter, hardware can't set it directly.

Best Regards,

Kerry

 

 

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Lukas_Frank
Contributor IV

Hi Dear @kerryzhou ,

Appreciate for your supports.

Best Regards.

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