Hi! I have an issue with FLEXSPI2. Board - MIMXRT1160-EVK; SDK 2.14 for GCC.
I use FLXSPI for communication with FPGA, QSPI mode. I implemented IP requests based on example flexspi_nor_edma_transfer. There are 2 functions: write 128-bytes block, and read 128-bytes block. And sometimes I can see on logic analyzer' captures that TX transaction breaks: I can see just part of transmitted data (48 or 64 bytes another number), and CS gets stuck at "0", but I receive DMA transaction complete event in DMA callback.
I added also interrupt handler to check errors from FLEXSPI, and I can see that I receive also "grant timeout event" (bit IPCMDGE in INTR reg).
My project is based on FreeRTOS. I have also working 1G ethernet, USB host, and configured SDRAM. I use default configurations for FLEXSPI and eDMA (use EDMA_GetDefaultConfig() and FLEXSPI_GetDefaultConfig()). I checked this issue also with code execution from ITCM, and it repeats.
I tried to increase/decrease rxWatermark / txWatermark, but it didn't make a difference.
I can't find any cause of this effect, or don't know how to handle it properly.
Also I can see another issue with FLEXSPI when I start to copy big buffers with DMA mem-to-mem (another DMA channel) in another task, where I configured lower interrupt priority. And sometimes I can see "stucking" of FLEXSPI TX transaction: with logic analyzer I can see sent command code, then long delay (~10 ms), and then data from buffer starts to transmit. It looks like latency: DMA ch "0" which handles FLEXSPI TX "waiting" for complete of DMA ch "2" (mem-to-mem, from/to external onboard SDRAM).
I can't find any Application Note about eDMA, and in Reference Manual I can't find number of eDMA engines or channel priorities.
Is it possible to configure highest priority for FLEXSPI' DMA channel?
I also attached QSPI captures for DSView with both of issues, you can see at the end of capture.
Thanks.
