About UB/LB Signals behavior when SEMC is used as SRAM-I/F

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About UB/LB Signals behavior when SEMC is used as SRAM-I/F

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george
Senior Contributor I

Hi all,

We are going to use SEMC as SRAM-I/F(ASYNC non-ADMUX w/ WAIT) to connect to FPGA.

Please tell me the behavior of the UB/LB signals.
Can you provide me with a timing diagram showing those behaviors?

BR,
George

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi George,

I received an update, you can take as reference see the LB#/UB# signals in ASYNC SRAM write in Non-ADMUX address mode.

FelipeGarcia_1-1635204627286.png

Best Regards,

Felipe

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi George,

These signals are Upper and Lower Byte select pins. SRAM will read or write upper or lower data byte depending on this signals. We do not have timing diagrams including these pins but you can find more information of this in your specific memory datasheet.

Have a great day,

Felipe

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george
Senior Contributor I

Dear @FelipeGarcia 

The device that connects to the RT1175 is an FPGA.
We have to configure the FPGA according to the RT1175 I/F specifications.
Therefore, we need to know the cycle-based signal transition.

Other signal timings seem to be variable by the registers, but it remains unclear where the signal transitions occur for UB and LB.

For example, in the following mode :

PRI_20210924-162706.bmp

At what timing in this figure the UB and LB signals transition?

And where is it when read ?

PRI_20210924-165459.bmp

BR,
George.

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi George,

Unfortunately, we do not have timing diagrams including these signals. However, just for reference you can check SRAM datasheets for example: https://www.issi.com/WW/pdf/65WV25616ALL_BLL.pdf

There you will find more info about timing and behavior of these signals.

Best regards,

Felipe

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george
Senior Contributor I

Hello @FelipeGarcia 

The documentation you presented to me allowed me to understand the behavior of UB/LB.

I think you can guarantee that UB / LB is valid during green period I added in red.
Is my understanding correct?

aw.pngar.png

BR,
George

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi @george,

Could you please provide what was the thinking behind this timing diagrams? Please be as detailed as possible.

Best regards,

Felipe

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george
Senior Contributor I

Hello @FelipeGarcia,

Sorry for the late reply.

The UB/LB I added may have been too extreme.
It may be necessary to extend the valid fields backward by one semc_clk.

My thoughts are as follows.

First, Write timing:
SRAM needs to capture UB/LB-gated DATA at WE# rising edge.
I think UB/LB needs setup and hold at WE# rising edge.

Second, Read timing:
SRAM needs to control the DATA output with UB/LB and OE, which requires setup and hold for the internal rxclkn rising edge.

Please tell me the valid period for which you can guarantee.

BR,

George

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi George,

To give you an update. We are still trying to get further information from IP owner. Once I get more information I will post it here.

Best regards,

Felipe

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george
Senior Contributor I

Hello @FelipeGarcia,

Thank you for your sincere response.

I will continue to wait for your reply.

BR,
George

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi George,

I received an update, you can take as reference see the LB#/UB# signals in ASYNC SRAM write in Non-ADMUX address mode.

FelipeGarcia_1-1635204627286.png

Best Regards,

Felipe

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george
Senior Contributor I

Hello @FelipeGarcia,

Sorry for the late reply.

Thank you for the update.

In other words, we understand that UB#/LB# is Low-Active between AS and WEH in the internal state.

Thanks,
George

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi George,

I will check internally if we have any information about this.

Best regards,

Felipe

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