Hi, I'm designing a custom board with the iMX RT 1176 MCU chip. I see some inconsistency regarding the required power sequencing, according to the MCU datasheet, and its actual implementation in the eval. board - MIMXRT1170-EVKB.
I'm talking about the VDDA_1P8 power rail that should be powered simultaneously as VDD_SOC_IN (MCU Datasheet Figure 4.). If both rails are powered by internal DCDC regulator outputs (DCDC_ANA for VDDA_1P8 and DCDC_DIG for VDD_SOC_IN), everything should be as shown in the power sequencing diagram.
The problem is that according to the evaluation board schematic, the VDDA_1P8 (called VDDA_1P8_IN in the schematic) rail is powered by an external LDO output (VDD_1V8), which is separate from power sequencing. So, the VDD_1V8 rail gets the power to the MCU (VDDA_ADC_1P8 and VDDA_1P8_IN) pins sooner than the internal DCDC is up and probably before VDD_SNVS and VDD_LPSR are powered on (or simultaneously, who knows)
Is the VDDA_1P8 part of the power sequencing, or can it be powered on regardless of whether other rails are already up?
Thanks!
