Hello NXP,
reference is made to an i.MX RT1175 running at 800MHz. The FlexSPI1 is using in OCTA mode with the following LUT table:
#define WRITE_CMD 0x0101
#define READ_CMD 0x0202
const uint32_t LUT_OctaSPI_DDR[CUSTOM_LUT_LENGTH] =
{
// (0) Write Array
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, (uint8_t)(WRITE_CMD >> 8),
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, (uint8_t)(WRITE_CMD & 0xFF)
),
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 32,
kFLEXSPI_Command_DATSZ_DDR, kFLEXSPI_8PAD, 16
),
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, (2*2+0), // 2N, 2N-1, 2N+1
kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 128
),
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, (1*2+1), // 2N, 2N-1, 2N+1
kFLEXSPI_Command_STOP, 0, 0
),
// (1) Read Array
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, (uint8_t)(READ_CMD >> 8),
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, (uint8_t)(READ_CMD & 0xFF)
),
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 32,
kFLEXSPI_Command_DATSZ_DDR, kFLEXSPI_8PAD, 16
),
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, (2*8-1), // 2N, 2N-1, 2N+1
kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 128
),
FLEXSPI_LUT_SEQ (
kFLEXSPI_Command_STOP, 0, 0,
0, 0, 0
)
};
The SPI clock (A_SCLK) is 33 MHz, that mean a DDR clock of 66 MHz. The rxSampleClock is set to kFLEXSPI_ReadSampleClkLoopbackFromSckPad.
Unfortunately the dummy cycle is only 4x A_SCLK. But the LUT is configured for 8. Here we can change the Dummy cycle in write access, but in a read access only 4 cycles are available.
Reference is made to the:
RT1170 Processor Reference Manual
Rev. 2, 06/2023
I have some problems to understand the Dummy cycle calculation.
In case of SDR mode, page 2335, Figure 30-8 with a operand value of 7, the dummy cycle count is 7 too. This is OK. In case of DDR mode, page 2336, Figure 30-9 with a operand value of 8, the dummy cycle count is 4. This is OK, because of DDR.
In DDR mode, page 2337, Figure 30-10, the calculation for the latency count N is (2*n-1) in the picture. My main focus is here 2*N. But I do not understand page 2338, Figure 30-11. Why here the calculation is 4*N? Is this a typo? Or can here the latency changed only in blocks of 4?
Btw, a FPGA is connected instead of a Flash memory.
Do you have any hints for us?
Best regards,
Michael
Hello,
on page 2331 I can found the information that the dummy cycle (DUMMY_RWDS_DDR) is depending of the RWDS (DQS) pin.
If the pin is high: (operand[7:0] × 4 - 1)
If the pin is low: (operand[7:0] × 2 - 1)
Furthermore on page 2334 I can find the following information:
“The FlexSPI controller checks the DQS pin input level at the fourth cycle after SCLK output toggling is enabled. The DQS pin is called RWDS in HyperBus specification.”
Page 2337, Figure 30-10:
Here the DQS is low => 2*N
Page 2338, Figure 30-11:
Here DQS is high => 4*N
But is the following description correct?
“The FlexSPI controller checks the DQS pin input level at the fourth cycle after SCLK output toggling is enabled.”
Here it is the fourth cycle after sfck, or the fourth edge from SCLK.
What is the correct description?
Is a dummy cycle really needed, or can the latency be complete controlled by the output of A_DQS?
Here we use a FPGA instead of a Flash. That mean the DQS will be clocked if the FPGA is ready.
Best regards,
Michael
