i.MX RT1170: how to design with PSRAM ( Xccela protocol )

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i.MX RT1170: how to design with PSRAM ( Xccela protocol )

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alexjiang
Contributor II

Hi,

We'd like design with Xccela protocal PSRAM on i.MX RT1170 platform.

We found i.MX RT1170 have two controller:

FlexSPI1: dual-channel  x4 bit,support individual x4 mode , parallel x8 mode; 

FlexSPI2:dual-channel x8bit, support individual x4/x8 mode,parallel x8/x16 mode;

 

1. We'd like use FlexSPI2  connect the x8bit Xccela PSRAM, and worked at  individual x8 mode. 

Whether NXP can well support the above use?

2.If we use FlexSPI2 connect a x16bit Xccela PSRAM(only one CE#),and connect the A_ss0 and B_ss0 both to PSRAM CE#(x16bit PSRAM only have one CE#),Whether it can work properly?

3.What is the maximum clock supported by FLexSPI?200MHz?

 

 

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elena_faventi1
Contributor II

I am a hardware designer,

I remember a problem that arose when I thought about using an octal flexram for my infotainment application. I was excited about the idea of ​​making a board with few layers for my application. However we found that there is a limit to the size of some buffers inside the flexspi controller in either direction so my idea was not suitable for video application. Maybe the flexspi controller was adequate to control ROM and less suitable for RAMs. I 'd be interested to know if some limits have been exceeded. I don't remember any other details about it. Hi!

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jeremyzhou
NXP Employee
NXP Employee

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Whether NXP can well support the above use?
-- To be prudent, I was wondering if you can upload the datasheet of the Xccela PSRAM.
2) 3.What is the maximum clock supported by FLexSPI?200MHz?
-- The maximum clock frequency is 166 MHz.
Have a great day,
TIC

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alexjiang
Contributor II

Hi,

1. please refer to the attachment about the x8bit Xccela PSRAM.

2. i.MX RT600 FlexSPI support CLKmax=200MHz? 

3.  If we use i.MX RT1170 FlexSPI2 connect a x16bit Xccela PSRAM(only one CE#),and connect the A_ss0 and B_ss0 both to PSRAM CE#(x16bit PSRAM only have one CE#),Whether it can work properly?

x16bit Xccale PSRAM pin:one CE#

3935705.jpg

 

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jeremyzhou
NXP Employee
NXP Employee

Hi,
Thanks for your reply.
1) i.MX RT600 FlexSPI support CLKmax=200MHz?
-- Yes.
2) If we use i.MX RT1170 FlexSPI2 connect a x16bit Xccela PSRAM(only one CE#),and connect the A_ss0 and B_ss0 both to PSRAM CE#(x16bit PSRAM only have one CE#),Whether it can work properly?
-- In my opinion, it's available to do that.
Have a great day,
TIC

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alexjiang
Contributor II

Hi,

the new x16bit PSRAM: only one CE# pin, and no RST# pin.

1.Is the following design ok?

x16bit PSRAM only uses low byte(ADQ0~7) to access CMD, but FlexSPI2 send CMD on portA and portB individually, whether the CMD send on port A and B are synchronized?

alexjiang_0-1635241318299.png

 

2. x16bit PSRAM uses the global reset CMD to reset the chip, no RST# pin.

  Whether the FlexSPI2 supports the global reset CMD?

alexjiang_1-1635241332446.png

 

 

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Alex-APMemory
Contributor I

Hi, 

We look at your case and we believe it should work.

However we can't find any Board in Lab capable to test it. 

In case you or NXP team could simulate it, we can support verilog model of 256Mb (APS256XXN-OBR-BG) or 512Mb (APS512XXN-OBR-BG) OPI x16 

If you try it, we are very much interested to get your feedback.

Thanks

Alex

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