UART3 overrun error occurs RT1020

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UART3 overrun error occurs RT1020

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hanmant
Contributor III

Hi,

I'm using uart3 interrupt of RT1020 ,i'm using uart3 for rs-485 communication and its speed is 3MBps.

Also, I'm using LPSPI4 CMSIS driver handler for other communication .

Individually uart3 works fine but after adding spi handler , it will start occurring Overrun.

Still im clearing overrun flag but why this flag is getting set .

Also ,one query when this flag set ,in this case will i receive all data or lost

Uart_status register.PNG

?

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mayliu1
NXP Employee
NXP Employee

Hi @hanmant ,

I use MIMXRT1020-EVK board  as edma_b2b_transfer_master, MIMXRT1064-EVK board as edma_b2b_transfer_slave.  

mayliu1_4-1732184845065.jpeg

 

I create a project based on  MIMXRT1020-EVK board, I set this board as I2C master, add UART TX, UART RX, totally using 4 DMA channels.   I modify some code  both of MIMXRT1020-EVK project  and MIMXRT1064-EVK project. 

The result is both projects run Okay.

mayliu1_5-1732184992668.png

So please check your code, the critical code I have shown you bellow. 

mayliu1_0-1732184067449.png

mayliu1_1-1732184078401.png

mayliu1_2-1732184103892.png

mayliu1_3-1732184133614.png

Please try it, and tell me to close this case.

If you still have question, Please create a new case.

 

BR

mayliu

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hanmant
Contributor III

Hi @mayliu1 ,

Thanks for reply.

Currently im using DMA uart. I'm using uart interrupt.

Please see below code snippet.

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hanmant
Contributor III
Hi @mayliu1 ,



Please Note Currently im not using DMA uart. I'm using uart interrupt.

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mayliu1
NXP Employee
NXP Employee

Hi @hanmant 

Thanks for your update information.

If you use UART interrupt to send and receive UART data, every UART byte will trigger a UART interrupt.

Your UART baud rate is very high(3MBps) and will cause frequent entry UART interrupt, which is unreasonable. 

I don't recommend you to use the UART interrupt when the UART baud rate is so high.

 

Best Regards

mayliu

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hanmant
Contributor III
Thanks for reply .
This overrun problem is coming after inclusion of spi cmsis handler.
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mayliu1
NXP Employee
NXP Employee

Hi @hanmant 

 

Question: This overrun problem is coming after inclusion of spi cmsis handler.

Answer: Due to the addition of spi cmsis handler, the entry of UART interrupt will be delayed and the UART data cannot be received in time.

 

BR

mayliu

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hanmant
Contributor III
So , I have to implement DMA uart then?
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mayliu1
NXP Employee
NXP Employee

Hi @hanmant 

 

I highly recommend you using the DMA UART , especially when UART baud rate is particularly high.

 

BR

mayliu

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hanmant
Contributor III

Hi @mayliu1 ,

As per your suggestion i configured uart in DMA but still see the losses.

I can see clear losses at receiver side(my receiver is another device comport).

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mayliu1
NXP Employee
NXP Employee

Hi @hanmant 

Thank you for your updated information.

Can you tell me when and where you call the DMA UART receive function interface?

"In the source files(lpuart_edma_transfer.c) you sent, I didn't see any calls to the DMA UART data receive interface."

Please try to verify it according to the steps shown below.
1: Set the DMA_UART interrupt priority to be higher than other modules.
2: Use ping pong buffer to receive UART data.

Wish it helps you.
If you still have question about it, please kindly let me know.

Best Regards

mayliu

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hanmant
Contributor III
Thanks for reply.
In this project i only send the data using DMA uart .
So the my receiver is Ti processor device.
I think priority does not matter in this example because here only DMA Uart is running.
I have tried to send 2 bytes of data but still same issue .
Give me solid solution to work this because this simple uart DMA transmission .
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mayliu1
NXP Employee
NXP Employee

Hi @hanmant 

 

Thank you for your updated information.

As you said, if you only send UART data, why you ask me UART overrun error happened.

UART overrun error is related with UART receive.

and if you want to send UART data, It is very simple, just call LPUART_SendEDMA.

mayliu1_0-1729663958271.png

BR

mayliu

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hanmant
Contributor III

Hi @mayliu1 ,

Thanks for reply.
As of now im not using uart receiver .
whatever i shared with is only uart transmit only (size 52 buffer)but i dont receive correct data on my Ti board using dma.

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mayliu1
NXP Employee
NXP Employee

Hi @hanmant 

 

I think I know the reason of the problem.

Continuous data transmission in your program can cause Ti board UART receiver overrun, resulting in abnormal data transfer.

I suggest adding a delay after sending 52 bytes UART data, Please try it.

I have tested and verified this 100 times on my end, and the data sending and receiving are consistent. 

mayliu1_1-1729667293341.png

 

Wish it helps you.
If you still have question about it, please kindly let me know.

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hanmant
Contributor III
Thanks for reply.
Can you please share your source code files.
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mayliu1
NXP Employee
NXP Employee

Hi @hanmant 

 

Just add a delay function, I have shown to you. 

SDK_DelayAtLeastUs(100000, CLOCK_GetFreq(kCLOCK_CpuClk));

1:In addition, I suggest you check whether the data format for UART sending and receiving is consistent.

2:Please confirm whether your NXP development board and TI development board share a common ground.

3:Please confirm whether the connection between UART transmission and reception is secure.

 

 

BR 

mayliu

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hanmant
Contributor III
Hi @mayliu,

Can you please tell me how to set Highest the Priority to DMA controller over CPU.
Also in DMA i want set the highest priority to UART receive and TX than SPI.
Please tell me the process and API's or any examples.
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mayliu1
NXP Employee
NXP Employee

Hi @hanmant ,

 

Thank you for your updated information.

I suggest you can use NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)function.

1: The first parameter is IRQn_Type:

It depends on your design, if UART3 using DMA channel 0(#define LPUART_TX_DMA_CHANNEL 0U), then the first parameter is DMA0_DMA16_IRQn.

 

2:The second parameter is priority, The lower value, the greater the priority  of the corresponding interrupt.

 

Best Regards

mayliu

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hanmant
Contributor III
Hi @mayliu,
I'm thinking add this way,
const edma_channel_Preemption_config_t Channel_preemption_config = {
.enableChannelPreemption = false,
.enablePreemptAbility = true,
.channelPriority = 14U
};
const edma_channel_Preemption_config_t Channel14_preemption_config = {
.enableChannelPreemption = false,
.enablePreemptAbility = true,
.channelPriority = 15U
};

EDMA_SetChannelPreemptionConfig(EXAMPLE_LPUART_DMA_BASEADDR,LPUART_TX_DMA_CHANNEL, &Channel_preemption_config);
EDMA_SetChannelPreemptionConfig(EXAMPLE_LPUART_DMA_BASEADDR, LPUART_RX_DMA_CHANNEL, &Channel14_preemption_config);
is it correct or not.
please confirm
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mayliu1
NXP Employee
NXP Employee

Hi @hanmant ,

Please review the differences between the following definitions and use them according to your needs.

EDMA_SetChannelPreemptionConfig: It is primarily used to configure the preemption priority of DMA channels, ensuring the most important task can be processed first, when multiple DMA tasks happened at the same time.

NVIC_SetPriority:  It is used to set the priority of interrupts, ensuring that high-priority interrupts can be responded to and processed by the CPU first when multiple interrupts happened at the same time.

Best Regards

mayliu

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hanmant
Contributor III
Hi @mayliu,
Thank you for reply
lpuart_config_t lpuartConfig;

lpuart_transfer_t sendXfer;
lpuart_transfer_t receiveXfer;
edma_config_t userConfig = {0};
uint32_t uiCnt = 0;



/* Initialize the LPUART. */
/*
* lpuartConfig.baudRate_Bps = 115200U;
* lpuartConfig.parityMode = kLPUART_ParityDisabled;
* lpuartConfig.stopBitCount = kLPUART_OneStopBit;
* lpuartConfig.txFifoWatermark = 0;
* lpuartConfig.rxFifoWatermark = 0;
* lpuartConfig.enableTx = false;
* lpuartConfig.enableRx = false;
*/
LPUART_GetDefaultConfig(&lpuartConfig);
lpuartConfig.baudRate_Bps = UART3_BAUDRATE;
lpuartConfig.enableTx = true;
lpuartConfig.enableRx = true;

LPUART_Init(DEMO_LPUART, &lpuartConfig, DEMO_LPUART_CLK_FREQ);


// Set NVIC priority for the DMA interrupt to highest priority
NVIC_SetPriority(DMA0_DMA16_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); // Highest priority for DMA0 interrupt
// DMA1_DMA17_IRQn

#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT
/* Init DMAMUX */
DMAMUX_Init(EXAMPLE_LPUART_DMAMUX_BASEADDR);
/* Set channel for LPUART */
DMAMUX_SetSource(EXAMPLE_LPUART_DMAMUX_BASEADDR, LPUART_TX_DMA_CHANNEL, LPUART_TX_DMA_REQUEST);
DMAMUX_SetSource(EXAMPLE_LPUART_DMAMUX_BASEADDR, LPUART_RX_DMA_CHANNEL, LPUART_RX_DMA_REQUEST);
DMAMUX_EnableChannel(EXAMPLE_LPUART_DMAMUX_BASEADDR, LPUART_TX_DMA_CHANNEL);
DMAMUX_EnableChannel(EXAMPLE_LPUART_DMAMUX_BASEADDR, LPUART_RX_DMA_CHANNEL);
#endif
/* Init the EDMA module */
EDMA_GetDefaultConfig(&userConfig);
#if defined(BOARD_GetEDMAConfig)
BOARD_GetEDMAConfig(userConfig);
#endif
EDMA_Init(EXAMPLE_LPUART_DMA_BASEADDR, &userConfig);
EDMA_CreateHandle(&g_lpuartTxEdmaHandle, EXAMPLE_LPUART_DMA_BASEADDR, LPUART_TX_DMA_CHANNEL);
EDMA_CreateHandle(&g_lpuartRxEdmaHandle, EXAMPLE_LPUART_DMA_BASEADDR, LPUART_RX_DMA_CHANNEL);
#if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
EDMA_SetChannelMux(EXAMPLE_LPUART_DMA_BASEADDR, LPUART_TX_DMA_CHANNEL, DEMO_LPUART_TX_EDMA_CHANNEL);
EDMA_SetChannelMux(EXAMPLE_LPUART_DMA_BASEADDR, LPUART_RX_DMA_CHANNEL, DEMO_LPUART_RX_EDMA_CHANNEL);
#endif
// Set DMA channel priorities
// EXAMPLE_LPUART_DMA_BASEADDR->DCHPRI[LPUART_TX_DMA_CHANNEL] = (EXAMPLE_LPUART_DMA_BASEADDR->DCHPRI[LPUART_TX_DMA_CHANNEL] & ~DMA_DCHPRI_CHPRI_MASK) | DMA_DCHPRI_CHPRI(15);
// EXAMPLE_LPUART_DMA_BASEADDR->DCHPRI[LPUART_RX_DMA_CHANNEL] = (EXAMPLE_LPUART_DMA_BASEADDR->DCHPRI[LPUART_RX_DMA_CHANNEL] & ~DMA_DCHPRI_CHPRI_MASK) | DMA_DCHPRI_CHPRI(15);


// EXAMPLE_LPUART_DMA_BASEADDR->DCHPRI0
const edma_channel_Preemption_config_t Channel_preemption_config = {
.enableChannelPreemption = false,
.enablePreemptAbility = true,
.channelPriority = 14U
};
const edma_channel_Preemption_config_t Channel14_preemption_config = {
.enableChannelPreemption = false,
.enablePreemptAbility = true,
.channelPriority = 15U
};

EDMA_SetChannelPreemptionConfig(EXAMPLE_LPUART_DMA_BASEADDR,LPUART_TX_DMA_CHANNEL, &Channel_preemption_config);
EDMA_SetChannelPreemptionConfig(EXAMPLE_LPUART_DMA_BASEADDR, LPUART_RX_DMA_CHANNEL, &Channel14_preemption_config);
/* Create LPUART DMA handle. */
LPUART_TransferCreateHandleEDMA(DEMO_LPUART, &g_lpuartEdmaHandle, LPUART_UserCallback, NULL, &g_lpuartTxEdmaHandle,
&g_lpuartRxEdmaHandle);
Im thinking to use this way .
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