I was hoping someone could explain the effect of the SAI MSB First (MF) field on the receipt of data via I2S.
In this case, does MSB still stand for most significant byte (and not most significant bit)?
My interpretation is the following:
MSB First (MF) specifies if the first byte received per word is the most significant or least significant.
Example:
16-bit words
1111 0000 0000 1111 is shifted out, from left to right
With the MSB First (MF) set to 1 (selecting MSB):
The sample value is 0xF00F
the receive buffer (in our little-endian system) reads:
Base Address: 0x0F
Base Address + 1: 0xF0
With the LSB First (MF) set to 0 (selecting LSB):
The sample value is 0x0FF0
The receive buffer (in our little-endian system) reads:
Base Address: 0xF0
Base Address + 1: 0x0F
Is this correct?
Solved! Go to Solution.
Hi Austin Wilhite,
You can check the RT reference manual about Figures 37-2 and 37-3, it means the Data in the FIFO can be aligned anywhere within the 32-bit wide register through the use of the First Bit Shifted configuration field, which selects the bit index (between 31 and 0) of the first bit shifted.
Wish it helps you!
If you still have questions about it, please kindly let me know.
Have a great day,
Kerry
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Can you explain how to interpret Figures 37-2 and 37-3? It's not clear to me what exactly they are attempting to illustrate.
Hi Austin Wilhite ,
After double check with our SAI expert, the MSB and LSB is significant bit, not byte.
The RT SAI in default is using LSB.
When you use the FIFO aligned within the 32bit wide register, you need to refer to this Figure:
Wish it helps you!
If you still have questions about it, please kindly let me know.
Have a great day,
Kerry
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- We are following threads for 7 weeks after the last post, later replies are ignored
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Kerry,
Although the RT SAI registers default to LSb, the SAI driver defaults to MSb.
Can you explain how to interpret Figures 37-2 and 37-3? It's not clear to me what exactly they are attempting to illustrate.
Hi Austin Wilhite,
You can check the RT reference manual about Figures 37-2 and 37-3, it means the Data in the FIFO can be aligned anywhere within the 32-bit wide register through the use of the First Bit Shifted configuration field, which selects the bit index (between 31 and 0) of the first bit shifted.
Wish it helps you!
If you still have questions about it, please kindly let me know.
Have a great day,
Kerry
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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