RT1170 Periodic DMA transfers (PIT vs GPT)

[yannickbt]

Hi,

I'm quite interested in the RT1170's capability to have periodic DMA transfers for e.g. feeding a DAC from a buffer without CPU intervention or stocking ADC data into a buffer.

I notice in the RM the PIT timer is designed specifically for this.

However it seems the Quad timers as well as PWM modules can generate periodic DMA requests to transfer to/from registers.

What would prevent me from programming a periodic DMA transfer with e.g. a quad timer, then use DMA channel linking using DLAST_SGA and then, after transfering timer register data, a new linked DMA request could be initiated that would for example transfer SPI data to a DAC.

Is that a possibility? Just trying to figure out how much versatile the DMA architecture is.

[mayliu1]

Hi @yannickbt ,

Thank you so much for your interest in our products and for using our community.

There are two main use cases.

Case 1:  Transfer a block of continuous memory data to a  not continuous memory space.

Case 2: Copying multiple segments of data(evenly spaced within a memory region)  to a continuous block  memory .

You can refer to SDK demo "evkbmimxrt1170_edma_scatter_gather_cm7".

If you want one DMA transfer done trigger next DMA transfer, I suggest you can use XBAR module.

Wish it helps you.
If you still have question about it, please kindly let me know.

Best Regards

mayliu

[yannickbt]

Thanks for answering mayliu.

What I'm looking for is exactly as you described : triggering multiple different DMA transfers one after the other from/to different peripherals.

I read about scatter gather before and I thought the DLAST_SGA field server exactly this purpose.

On e.g. Atmel SAM MCUs or STM32, the DMA controller can be configured in "linked list" mode where so DMA transfers can be arranged this way (for example in a cyclic manner) :

dma1 -> dma2 -> dma3 -> dma1

Each dma descriptor has its own channel config that is applied upon loading the descriptor.

Each dma transfer can have a different trigger and transfer data from/to different addresses or peripherals.

From my understanding, the NXP RT DMA architecture allows the same with major loops and TCDs, and the field that links a TCD to another would be DLAST_SGA, no?

If that is not the case how could XBAR be used to do a similar scheme?

[mayliu1]

HI @yannickbt ,

Thanks for your reply.

Question:

dma1 -> dma2 -> dma3 -> dma1

Each dma descriptor has its own channel config that is applied upon loading the descriptor.

Each dma transfer can have a different trigger and transfer data from/to different addresses or peripherals.

From my understanding, the NXP RT DMA architecture allows the same with major loops and TCDs, and the field that links a TCD to another would be DLAST_SGA, no?

Answer: I'm quite confused about your question.

I think you can refer SDK demo "evkmimxrt1170_edma_scatter_gather", 

One DMA channel  could use 2 TCD  slots to realized scatter_gather func.

As  you said "dma1 -> dma2 -> dma3 -> dma1",  are these DMA are different channel?

I think if you want to know the specific working principle of DMA and DLAST_SGA, you can do a  tests and verifications on your MIMXRT1170-EVKB board.

Question:

If that is not the case how could XBAR be used to do a similar scheme?

Answer:

XBAR can do a similar scheme, Please refer to Chapter 83
Inter-Peripheral Crossbar Switch A (XBARA) in MIMXRT1170RM.

BR

mayliu

[yannickbt]

Hi, sorry for not being too clear.

I don't have any NXP hardware at hand so I cannot test SDK demos. We are considering migrating to NXP though. Do you have a link to ""evkmimxrt1170_edma_scatter_gather" that I can access through the net?

When I said

dma1 -> dma2 -> dma3 -> dma1

Those were descriptors. What I meant is that on some architectures, dma descriptors can be "chained" by acting like a linked list. Each dma descriptor has a pointer on the next dma descriptor once the transfer is completed. A dma descriptor can also have a "config" member for example, which can reconfigure the channel for e.g. doing a transfer on a different peripheral with a different trigger. So when the DMA controller finishes a transfer on e.g. "UART1 triggered by TMR1", it can then fetch a new descriptor to wait for a transfer on "SPI1 triggered by TMR2" or something along those lines.

What I meant was that (for a circular transfer list of 3 different peripherals, we'd have each descriptor constructed as pointing to the next one like this) :

dma_desc1 -> dma_desc2 -> dma_desc3 -> dma_desc1

Note we are talking about the same DMA channel. Not multiple channels. Its just that the same channel can be reconfigured by descriptor chaining to wait for different triggers and transfer on different peripherals each time it fetches a new descriptor pointer from the previous descriptor.

Now regarding NXP IMX RT processors, the essence of my question is... I wonder what is equivalent to that? Is that Scatter-Gather? From what Isee when ESG is 1 in the TCD, DLASTSGA can be used to point to a new TCD. So that means source and destination addresses can be reconfigured on the same channel. However I'm not sure how the trigger can also be changed each time a transfer is completed, *without processor intervention*.

If I want to do (all on the same DMA channel, no CPU intervention) :

- Send 32bytes from memory to USART1, triggered by QTIMER1 compare match

then

- Send 32 bytes from memory to LPSPI1, triggered by QTIMER2 compare match

then

- Send 32 bytes from memory to USART2, triggered by QTIMER3 compare match

Repeat

How can I do that with RT MCUs?

[mayliu1]

Hi @yannickbt 

Thanks for your update information.

Question: I don't have any NXP hardware at hand so I cannot test SDK demos. We are considering migrating to NXP though. Do you have a link to ""evkmimxrt1170_edma_scatter_gather" that I can access through the net?

Answer:  I think you can refer to this link 

https://github.com/nxp-mcuxpresso/mcux-sdk-examples/tree/main/evkbmimxrt1170/driver_examples/edma/sc...

As for the rest question, Please give me sometime to check.

Wish it helps you.

BR

mayliu