IMXRT1062 Hardfault Reading CAN3 ERFCR Register

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IMXRT1062 Hardfault Reading CAN3 ERFCR Register

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michaelsmorto
Contributor IV

According to the 1060RM setting the ERFCR will enable the Enhanced FIFO.  However when I try to even read the register in the FLEXCAN  example it throws a hard fault.  When I tried it in my own application on a imxrt1062 I also get a hard fault at that register address.  Needless to say I can't set it either.

So the question is, what is the cause of the issue and is Enhanced FIFO even enabled and the RM is incorrect?

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Michael Smorto

  Before you call base->ERFCR |= CAN_ERFCR_ERFEN(1);  

  Please note this point:

MCR[RFEN] must be cleared so that Enhanced Rx FIFO is enabled.

I find your code didn't add the MCR[RFEN] clear code, please add it and try it again.

 BTW, it's better to provide the source code, because I even can't find your definition about:flexcan_fd_fifo_filter_b01_t


Have a great day,
Kerry

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michaelsmorto
Contributor IV

Hi Kerry

I converted the whole app to run on the 1062EVB instead of what I sent you.  Please see attached zip.  Maybe easier for you to use.

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TomE
Specialist II

Did you check to see what other registers in the Flexcan controller can be read? Which ones can and which ones can't may point to the problem.

> base->ERFCR |= CAN_ERFCR_ERFEN(1); 

Are you sure the compiler isn't turning that into a bit or byte operation? Can you disassemble it and see what it is really doing?


The definition of the address of "ERFCR" also relies on a lot of definitions in the headers being right, and six sets of "uint8_t RESERVED_N[MMM]" being parsed properly. Can you print the address you're actually accessing to see if it is correct?

Tom

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michaelsmorto
Contributor IV

Hi Tom

Well right before the fault I print several registers as a sanity check of the configuration:

MCR ---- a0080f

CTRL1 ---- 15a2021

TIMER ---- cdd

IMASK1 ---- 0

IFLAG1 ---- 0

IFLAG2 ---- 0

CTRL2 ---- b30000

ESR2 ---- 6000

CRCR ---- 0

ESR2 ---- 6000

FDCTRL ---- 80008300

CLOCKS

CCM_CSCMR2 ---- 13192e0e

CCM_CCGR7 ---- fffffff3

Also, I have run the CANFD examples without a problem so know at least the normal registers are working.

As for "> base->ERFCR |= CAN_ERFCR_ERFEN(1); "   I tried it this was as well "> base->ERFCR = CAN_ERFCR_ERFEN(1); " and will still get the fault.

Ok you got me on this one: "six sets of "uint8_t RESERVED_N[MMM]" being parsed properly. Can you print the address you're actually accessing to see if it is correct?"  - this is what I get

ERFCR -------401d8c0c  which is correct to the manual.

Can I ask you all another question - i tried adding printf in the driver itself but the compiler complained - can you tell me how to do that?

Thanks

Mike

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TomE
Specialist II

> Can I ask you all another question - i tried adding printf in the driver itself but

> the compiler complained - can you tell me how to do that?

I think you edited the post because there are changes between it and the email notification I received. I'm guessing you found the "%p" option in "printf()" or cast the address to an int or something.

I don't know what operating system you're running (assuming it isn't Linux on these parts), so don't know what calls they're using for this. How to debug-print from a driver should be documented somewhere. Assuming it isn't, or you can't find it, read the other drivers until you can find some debug printing that a previous author left in there, and copy that. That driver may be including a header that is required for the functions it uses, so you'll have to check through the header sources to find which ones are needed, or just include all of them (that the other driver does) and start deleting them to find out which one or ones it needs.


Tom

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Michael Smorto,

   Thank you for your new code.

  Do you port your code to the SDK canfd_interrupt project, now, could you tell me, what the detailed problem in your attachment, still enter the hard fault? Which code line will enter the hard fault, then I will help you to test it on my board.


Have a great day,
Kerry

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michaelsmorto
Contributor IV

Hi Kerry

Just reran.  Yep it hard faults at enabling the enhanced FIFO.  Here's a little screenshot:

Capture.JPG

I know there are other problems with my coding for Enhanced FIFO, but need to get past this first.  Thanks for all your help.

Respectfully

Mike

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michaelsmorto
Contributor IV

Hi All

Haven't heard anything on this issue for awhile so was wondering if there is any status or is it just not possible to do FIFO FD on the 1062.

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michaelsmorto
Contributor IV

Hi Kerry

Sorry I didn't get back to you sooner but wrapped up in some other testing yesterday.  Anyway, I cleared MCR[FREN] bit and double checked that it was cleared by outputting the register in binary.  Matter of before clearing the bit I checked and it was already cleared.  But anyway, I do have to advise you that I already know that I am sure there are errors in my implementation for Enhanced FIFO but figured it would debug those going forward.

Anyway here is the whole source code. 

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TomE
Specialist II

Can you read the registers at offset zero? Can you read all the registers from 0x00 to 0x50?

... the MBs from 0x80 to 0x47f?

... the RXIMRs from 0x880 to 0x87c?

... 0xbf0 to 0xbfc?

... 0xc00 to 0xc14?

... 0xc30 to 0xd2c?

... 0x2000 - 0x204c?

... 0x3000 - 0x31fc?

Are you sure "CAN_MCR[RFEN]" isn't set?

Does the module have all of its clocks generated and enabled (Table 13-5 and CCM_CCGR7?

Tom

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