How to reduce the time interval of SEMC continuous read operations

[yangzeyong]

RT1064 accesses FPGA according to asynchronous SRAM interface. The time interval between two read operations is approximately 100ns. How to reduce this time interval?

The SRAMCR0/1/2 register in the SEMC controller cannot set the minimum time interval for two CS #.

How to solve this problem? Thanks

[Omar_Anguiano]

Hello
I hope you are well.

The only option to reduce this interval is the CEITV register for SRAM configuration. The reason for the longer interval could be limited to the module design however some other variables could be involved, e.g. if there are more devices connected to the interface apart from SRAM, BMCR values.

Best regards,
Omar

[yangzeyong]

I have configured the CEITV of SRAMCR2 to 0. Under the same configuration, the time interval between two write operations is about 20ns.

Why is the time interval between read operations much longer than write operations?