I am currently facing the following problem (using an i.MX 8MP):
During boot, the clock going to the lan8720 is being disabled for ~500ms. After that, the clock comes back but there is no reset. This can cause strange behavior (100 mbit not available, only 10 mbit). I am able to reproduce this issue.
I think it is the same issue as here: https://community.nxp.com/t5/i-MX-Processors/imx6ull-doesn-t-reset-LAN8720A-after-clk-enable/m-p/128...
The problem comes from: https://source.codeaurora.org/external/imx/linux-imx/commit/drivers/net/phy/smsc.c?h=lf-5.10.y&id=d6...
When I revert this patch, the issue goes away (Reset will come when clock is re-enabled - measured with oscilloscope - I attached my measurements as images).
However, I want to properly fix this problem and not revert this patch.
My dts currently looks like this:
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
fsl,magic-packet;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <0>, <50000000>, <100000000>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy-smsc@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
clocks = <&clk IMX8MP_CLK_ENET_PHY_REF>;
/*
* 100MBit/s ethernet with smsc phy
* detection does not work properly between two devices
* with same phy and enabled energy detect mode.
* disable it
*/
smsc,disable-energy-detect;
/* phy reset */
reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
reset-names = "phy";
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
status = "okay";
};
};
};
[...]
ethphy1: ethernet-phy-smsc@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
clocks = <&clk IMX8MP_CLK_ENET_QOS>; //I also tried <&clk IMX8MP_CLK_ENET_REF> and <&clk IMX8MP_CLK_ENET1_ROOT>
[...]
Can someone help me with this?
