imx8mp CSI-2 frame start issue

[Jayden_Soon]

I am developing a 2-channel camera with DART-MX8M-PLUS.

CAM -> PR2000K(HD Receiver with MIPI output) -> imx8mp

PR2000K only supports clock continuous mode. No non-continuous mode.

csi2-0 works normally, but csi2-1 cannot get a start frame. Strangely, sometimes it works.

Below are the dts file settings.

pr2000k_mipi1: pr2000k_mipi@5c {   compatible = "pixelplus,pr2000k";   reg = <0x5c>;   clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;   clock-names = "xclk";   csi_id = <1>;   mipi_csi;   status = "okay";   port {     pr2000k_mipi_1_ep: endpoint {     remote-endpoint = <&mipi_csi1_ep>;     data-lanes = <1 2 3 4>;     clock-lanes = <0>;   };  }; }; pr2000k_mipi0: pr2000k_mipi@5f {   compatible = "pixelplus,pr2000k";   reg = <0x5f>;   clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;   clock-names = "xclk";   csi_id = <0>;   mipi_csi;   status = "okay";   port {     pr2000k_mipi_0_ep: endpoint {     remote-endpoint = <&mipi_csi0_ep>;     data-lanes = <1 2 3 4>;     clock-lanes = <0>;   };  }; };

&mipi_csi_0 {   #address-cells = <1>;   #size-cells = <0>   status = "okay";   port@0 {     reg = <0>;     mipi_csi0_ep: endpoint {     remote-endpoint = <&pr2000k_mipi_0_ep>;     data-lanes = <4>;     csis-hs-settle = <3>;     csis-clk-settle = <0>;     csis-wclk;   };  }; }; &mipi_csi_1 {   #address-cells = <1>;   #size-cells = <0>   status = "okay";   port@1 {     reg = <1>;     mipi_csi1_ep: endpoint {     remote-endpoint = <&pr2000k_mipi_1_ep>;     data-lanes = <4>;     csis-hs-settle = <3>;     csis-clk-settle = <0>;     csis-wclk;   };  }; };

Debug message of imx8-mipi-csi2-sam.c

csi2-1 cannot get a start frame like below.

[ 167.160218] mxc-mipi-csi2.0: mipi_csis_s_stream: 1, state: 0x0 [ 167.160329] mxc-mipi-csi2.0: mipi_csis_imx8mp_phy_reset: bus fmt is 12 bit ! [ 167.160368] mxc-mipi-csi2.0: fmt: 0x2006, 1280 x 960 [ 167.160405] mxc-mipi-csi2.0: Frame Start: 1 [ 167.160410] mxc-mipi-csi2.0: status: 01000000 [ 167.176222] mxc-mipi-csi2.0: --- mipi_csis_s_stream --- [ 167.176234] mxc-mipi-csi2.0: CSIS_VERSION[0]: 0x03060301 [ 167.176241] mxc-mipi-csi2.0: CSIS_CMN_CTRL[4]: 0x00004b05 [ 167.176247] mxc-mipi-csi2.0: CSIS_CLK_CTRL[8]: 0x000f0000 [ 167.176252] mxc-mipi-csi2.0: CSIS_INTMSK[10]: 0x0fffff1f [ 167.176258] mxc-mipi-csi2.0: CSIS_INTSRC[14]: 0x00000000 [ 167.176264] mxc-mipi-csi2.0: CSIS_DPHYSTATUS[20]: 0x00000000 [ 167.176270] mxc-mipi-csi2.0: CSIS_DPHYCTRL[24]: 0x0300001f [ 167.176276] mxc-mipi-csi2.0: CSIS_DPHYBCTRL_L[30]: 0x000001f4 [ 167.176283] mxc-mipi-csi2.0: CSIS_DPHYBCTRL_H[34]: 0x00000000 [ 167.176289] mxc-mipi-csi2.0: CSIS_DPHYSCTRL_L[38]: 0x00000000 [ 167.176295] mxc-mipi-csi2.0: CSIS_DPHYSCTRL_H[3c]: 0x00000000 [ 167.176301] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH0[40]: 0x00001078 [ 167.176306] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH1[50]: 0x000008fd [ 167.176313] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH2[60]: 0x000008fe [ 167.176319] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH3[70]: 0x000008ff [ 167.176325] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH0[44]: 0x03c00500 [ 167.176330] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH1[54]: 0x80008000 [ 167.176336] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH2[64]: 0x80008000 [ 167.176342] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH3[74]: 0x80008000 [ 167.176348] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH0[48]: 0x00000000 [ 167.176354] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH1[58]: 0x00000000 [ 167.176359] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH2[68]: 0x00000000 [ 167.176365] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH3[78]: 0x00000000 [ 167.176371] mxc-mipi-csi2.0: --- mipi_csis_s_stream --- [ 167.176376] mxc-mipi-csi2.0: GPR_GASKET_0_CTRL[60]: 0xffff8000 [ 167.176384] mxc-mipi-csi2.0: GPR_GASKET_0_HSIZE[64]: 0xffff8000 [ 167.176389] mxc-mipi-csi2.0: GPR_GASKET_0_VSIZE[68]: 0xffff8000 [ 167.192412] mxc-mipi-csi2.0: Frame End: 1 [ 167.192426] mxc-mipi-csi2.0: status: 00100000 [ 167.193739] mxc-mipi-csi2.0: Frame Start: 2 [ 167.193752] mxc-mipi-csi2.0: status: 01000000 [ 167.225753] mxc-mipi-csi2.0: Frame End: 2 [ 167.225768] mxc-mipi-csi2.0: status: 00100000 [ 167.227075] mxc-mipi-csi2.0: Frame Start: 3 [ 167.227090] mxc-mipi-csi2.0: status: 01000000

[ 202.392216] mxc-mipi-csi2.1: mipi_csis_s_stream: 1, state: 0x0 [ 202.392333] mxc-mipi-csi2.1: mipi_csis_imx8mp_phy_reset: bus fmt is 12 bit ! [ 202.392372] mxc-mipi-csi2.1: fmt: 0x2006, 1280 x 960 [ 202.408216] mxc-mipi-csi2.1: --- mipi_csis_s_stream --- [ 202.408228] mxc-mipi-csi2.1: CSIS_VERSION[0]: 0x03060301 [ 202.408235] mxc-mipi-csi2.1: CSIS_CMN_CTRL[4]: 0x00004b05 [ 202.408241] mxc-mipi-csi2.1: CSIS_CLK_CTRL[8]: 0x000f0000 [ 202.408246] mxc-mipi-csi2.1: CSIS_INTMSK[10]: 0x0fffff1f [ 202.408252] mxc-mipi-csi2.1: CSIS_INTSRC[14]: 0x00000000 [ 202.408258] mxc-mipi-csi2.1: CSIS_DPHYSTATUS[20]: 0x000000f2 [ 202.408266] mxc-mipi-csi2.1: CSIS_DPHYCTRL[24]: 0x0300001f [ 202.408271] mxc-mipi-csi2.1: CSIS_DPHYBCTRL_L[30]: 0x000001f4 [ 202.408279] mxc-mipi-csi2.1: CSIS_DPHYBCTRL_H[34]: 0x00000000 [ 202.408285] mxc-mipi-csi2.1: CSIS_DPHYSCTRL_L[38]: 0x00000000 [ 202.408291] mxc-mipi-csi2.1: CSIS_DPHYSCTRL_H[3c]: 0x00000000 [ 202.408296] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH0[40]: 0x00001078 [ 202.408302] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH1[50]: 0x000008fd [ 202.408308] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH2[60]: 0x000008fe [ 202.408314] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH3[70]: 0x000008ff [ 202.408322] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH0[44]: 0x03c00500 [ 202.408327] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH1[54]: 0x80008000 [ 202.408335] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH2[64]: 0x80008000 [ 202.408341] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH3[74]: 0x80008000 [ 202.408347] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH0[48]: 0x00000000 [ 202.408353] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH1[58]: 0x00000000 [ 202.408358] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH2[68]: 0x00000000 [ 202.408365] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH3[78]: 0x00000000 [ 202.408371] mxc-mipi-csi2.1: --- mipi_csis_s_stream --- [ 202.408376] mxc-mipi-csi2.1: GPR_GASKET_0_CTRL[60]: 0xffff8000 [ 202.408382] mxc-mipi-csi2.1: GPR_GASKET_0_HSIZE[64]: 0xffff8000 [ 202.408388] mxc-mipi-csi2.1: GPR_GASKET_0_VSIZE[68]: 0xffff8000

https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-dual-MIPI-camera-CSI-2-1-not-leaving-ULPS-s... 

This is similar to the post above.

Are both 2 channels not captured in continuous mode?

Should I redesign with a different receiver chip?

Thanks in advance.

Best regards,

Jayden

[Sanket_Parekh]

Hi @Jayden_Soon 

I hope you are doing well

Kindly mention your BSP version.

Are you using the csi2-0 and csi2-1 simultaneously?

Thanks & Regards,

Sanket Parekh

[Jayden_Soon]

Hi Sanket,

SOM : DART-MX8M-PLUS

BSP : Yocto mx8mp-yocto-kirkstone-5.15-2.0.x-v1.2

I'm trying to use the csi2-0 and csi2-1 simultaneously.

Thanks.

Best regards,

Jayden

[Sanket_Parekh · Accepted solution]

Hi @Jayden_Soon,

I hope you are doing well.

Both continuous and non-continuous modes are supported on IMX8MP. But as mentioned in the document AN13857 section 6.4 Debug tips,

"Note: i.MX 8MM, i.MX 8MN, and i.MX 8MP require the connected camera to work in the LP state before
enabling the Rx DPHY. But if the camera works in continuous clock mode, the clock lane may always be in the
HS mode. In this case, Rx DPHY may not detect the HS mode and wrongly remains in the stop or ULPS state."

Hence, it is recommended to use the clock in non-continuous mode.

Thanks & Regards,
Sanket Parekh

[Jayden_Soon]

Hi Sanket,

PR2000K(HD Receiver) only supports clock continuous mode.

It's hard to solve it and looks like I need a little more study.

Thank you for reply.

Best regards,

Jayden

[Sanket_Parekh]

Hi @Jayden_Soon 

I hope you are doing well.

Is there any update from your side?

If there isn't any query should I proceed to close this thread?

Thanks & Regards

Sanket Parekh