Hi,
I have a custom board imx8mm. I am trying to enable the PCI1
This is on kernel: 5.10.
Is failing here. I am into this for 3 days already. I tried so many variants for the dtsi and I cannot pass this error
XXX Failed to get 'pciephy' reset control
[ 3.578885] imx6q-pcie 33800000.pcie: XXX imx6_pcie_VARIANT = 5 XX
[ 3.612272] imx6q-pcie 33800000.pcie: reset_get exclusive failed for pciephy
[ 3.624251] imx6q-pcie 33800000.pcie: ?? XXX Failed to get 'pciephy' reset control -517
case IMX7D:
if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
imx6_pcie->controller_id = 1;
imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
"pciephy");
if (IS_ERR(imx6_pcie->pciephy_reset)) {
dev_err(dev, "?? XXX Failed to get 'pciephy' reset control %d\n",
PTR_ERR(imx6_pcie->pciephy_reset));
return PTR_ERR(imx6_pcie->pciephy_reset);
}
My schematic is: (is GPIO expander not pci expander Sorry)
My dts file is:
/dts-v1/;
#include <dt-bindings/misc/nad-nmb.h>
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/clock/imx8mq-clock.h>
#include "imx8mm-pinfunc.h"
#include "imx8mq-pinfunc.h"
#define MX8MMN(a, b) MX8MM_##a b
#define IMX8MMN(a) IMX8MM_##a
/ {
/* ... */
// ----------------------- PCIE
pcie0: pcie@33800000 {
///-xx compatible = "fsl,imx8mq-pcie", "snps,dw-pcie","fsl,imx7d-pcie-phy";
compatible = "fsl,imx8mm-pcie", "snps,dw-pcie";
reg = <0x0 0x33800000 0x0 0x400000>, // host config space 4M
<0x0 0x32f00000 0x0 0x10000>, // IMX_REFERENCE_MANUAL page 109*/
<0x0 0x1ff00000 0x0 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>; // was 3
#size-cells = <2>;
device_type = "pci";
///-xx bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
interrupt-names = "msi"; ///-xx, "dma";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
ctrl-id = <0>;
// --x power-domains = <&pcie_pd>;
power-domains = <&pgc_pcie>; // my power domain
resets = <&src IMX8MQ_RESET_PCIEPHY>,//<&gpio_expander_out 8 0>
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, //IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "clkreq", "turnoff";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
//fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "okay";
};
/* ... */
};
&nmb {
/* ... */
// ----------------------- PCIE
export-names =
"reset-pcie",
"enable-pcie";
export-gpios =
<&gpio_expander_out 8 0>,
<&gpio_expander_out 5 0>;
export-flags =
<NMB_GPIO_OUT_LOW>,
<NMB_GPIO_OUT_LOW>;
/* ... */
};
&iomuxc {
// ----------------------- PCIE
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
// ----------------------- PCIE
pinctrl_pcie0: pcie0grp {
fsl,pins = <
#define GP_PCIE0_RESET <&gpio_expander_out 8 0>
//MX8MMN(IOMUXC_SAI3_TXFS_GPIO4_IO31, 0x100)
#define GP_PCIE0_DISABLE <&gpio_expander_out 5 0>
//MX8MMN(IOMUXC_GPIO1_IO04_GPIO1_IO4, 0x100)
>;
};
};
// ----------------------- PCIE
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
disable-gpio = GP_PCIE0_DISABLE;
reset-gpio = GP_PCIE0_RESET;
ext_osc = <0>;
status = "okay";
};
Thank you.
1 Solution
