Hi all
I find the CPU frequence could not be 996000, here is the cpu-info:
cpufreq-info
cpufrequtils 008: cpufreq-info (C) Dominik Brodowski 2004-2009
Report errors and bugs to cpufreq@vger.kernel.org, please.
analyzing CPU 0:
driver: imx6q-cpufreq
CPUs which run at the same hardware frequency: 0 1
CPUs which need to have their frequency coordinated by software: 0 1
maximum transition latency: 65.0 us.
hardware limits: 396 MHz - 792 MHz
available frequency steps: 396 MHz, 792 MHz
available cpufreq governors: interactive, conservative, userspace, powersave, ondemand, performance
current policy: frequency should be within 396 MHz and 792 MHz.
The governor "performance" may decide which speed to use
within this range.
current CPU frequency is 792 MHz (asserted by call to hardware).
cpufreq stats: 396 MHz:1.15%, 792 MHz:98.85% (756)
analyzing CPU 1:
driver: imx6q-cpufreq
CPUs which run at the same hardware frequency: 0 1
CPUs which need to have their frequency coordinated by software: 0 1
maximum transition latency: 65.0 us.
hardware limits: 396 MHz - 792 MHz
available frequency steps: 396 MHz, 792 MHz
available cpufreq governors: interactive, conservative, userspace, powersave, ondemand, performance
current policy: frequency should be within 396 MHz and 792 MHz.
The governor "performance" may decide which speed to use
within this range.
current CPU frequency is 792 MHz (asserted by call to hardware).
cpufreq stats: 396 MHz:1.15%, 792 MHz:98.85% (756)
But the device tree has defined the 996Mhz:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1150000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>,
<&clks IMX6QDL_CLK_PLL1>,
<&clks IMX6QDL_PLL1_BYPASS>,
<&clks IMX6QDL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys", "pll1",
"pll1_bypass", "pll1_bypass_src";
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
Is there any condition for that, on hardware or kernel configure?
Best regards
Mihan
