imx6 DDR_SEL

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imx6 DDR_SEL

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andrewdyer
Contributor III

In the i.MX6 reference manual [1] section 37.4.289 (IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET) it says the DDR_SEL field should be '11' for DDR3.  Value '00' is marked as reserved.


Looking at the code for DRAM setup u-boot from the Freescale git repository[2], it sets the bits to '00' (reserved).  I also see this as the recommended setting in the DDR3 setup spread sheet[3].  Which value for those bits is the correct one?

[1] i.MX 6Solo/6DualLite Applications Processor Reference Manual
Document Number: IMX6SDLRM Rev. 1, 04/2013

[2] uboot-imx.git - Freescale i.MX u-boot Tree

[3] I.MX6DQSDL DDR3 Script Aid V0.10 https://community.nxp.com/docs/DOC-94917

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TheAdmiral
NXP Employee
NXP Employee

Hi Andrew,

The Rev 2 version of the i.MX 6DQ Reference Manual correctly describes this register field as:

00  DDR3_LPDDR2 - DDR2 and LPDDR2 mode.
01  Reserved1 - Reserved

10  Reserved2 - Reserved

11  Reserved3 - Reserved

A CQ ticket has been submitted to update the other Reference Manuals in the i.MX 6 familiy to read the same way.

The DRAM_RESET pin is not a true high speed pin. It is either low when the DDR is not in operation, or it is high once the DDR has been initialized.

The correct setting for this pin is '00'.

Cheers,

Mark

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TheAdmiral
NXP Employee
NXP Employee

Hi Andrew,

The Rev 2 version of the i.MX 6DQ Reference Manual correctly describes this register field as:

00  DDR3_LPDDR2 - DDR2 and LPDDR2 mode.
01  Reserved1 - Reserved

10  Reserved2 - Reserved

11  Reserved3 - Reserved

A CQ ticket has been submitted to update the other Reference Manuals in the i.MX 6 familiy to read the same way.

The DRAM_RESET pin is not a true high speed pin. It is either low when the DDR is not in operation, or it is high once the DDR has been initialized.

The correct setting for this pin is '00'.

Cheers,

Mark

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