imx25 interrupt vector table

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imx25 interrupt vector table

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rbruce
Contributor II

A package named m25pdk_led was forwarded to me as a result of a previous post on this forum.  It provides an example of how to create a program that executes in imx25 internal RAM.  I have used this package as a basis to create several serial downloadable, internal RAM resident, diagnostic programs.  I would like to add additional diagnostics that would require processing interrupts, so I have been looking at the file crt_for_HAB.s, part of the m25pdk_led package.  A portion of this file is included below.  It places an interrupt vector table immediately following the Flash Header.  The program that includes this file is loaded at 0x78002000, so the vector table appears to be located at 0x78002020.  I have a rudimentary question:  The ARM interrupt vector table is typically located at memory address zero, but that is within the imx25 ROM area.  How does the vector table in the code loaded in internal RAM override the vector table at address zero?

   .section .vectors,"ax"

   .code 32


/* flash header  - should be placed before main image */  

app_code_jump_vector : .word  ResetHandler

app_code_barker : .word 0

app_code_csf : .word 0

dcd_ptr_ptr : .word app_code_csf

.word 0

.word 0

.word 0

.word 0

  

/****************************************************************************/

/*               Vector table and reset entry                               */

/****************************************************************************/

_vectors:

   ldr pc, ResetAddr    /* Reset                 */

   ldr pc, UndefAddr    /* Undefined instruction */

   ldr pc, SWIAddr      /* Software interrupt    */

   ldr pc, PAbortAddr   /* Prefetch abort        */

   ldr pc, DAbortAddr   /* Data abort            */

   ldr pc, ReservedAddr /* Reserved              */

   ldr pc, IRQAddr      /* IRQ interrupt         */

   ldr pc, FIQAddr      /* FIQ interrupt         */


ResetAddr:     .word ResetHandler

UndefAddr:     .word UndefHandler

SWIAddr:       .word SWIHandler

PAbortAddr:    .word PAbortHandler

DAbortAddr:    .word DAbortHandler

ReservedAddr:  .word 0

IRQAddr:       .word IRQHandler

FIQAddr:       .word FIQHandler

     ...

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Yuri
NXP Employee
NXP Employee

The exception vectors located at the start of internal ROM are used to map all

the ARM exceptions (except the reset exception) to a duplicate exception vector

table in iRAM, beginning from 0x7801_FFC0 address. During the boot phase, the

iRAM vectors point to the serial downloader in iROM. After boot the OS loader can

overwrite the vectors as required. Enclosed is an example - please pay attention on
function "interrupt_init()".

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Yuri
NXP Employee
NXP Employee

The exception vectors located at the start of internal ROM are used to map all

the ARM exceptions (except the reset exception) to a duplicate exception vector

table in iRAM, beginning from 0x7801_FFC0 address. During the boot phase, the

iRAM vectors point to the serial downloader in iROM. After boot the OS loader can

overwrite the vectors as required. Enclosed is an example - please pay attention on
function "interrupt_init()".

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rbruce
Contributor II

Thanks for the example.  I'll try it out.

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