i need to run a m4 application.bin from 0x88000000 (ddr)
From yocto, i created a imx-boot bbappend to use my "application.bin" and i selected the target flash_linux_m4_ddr, btw, board is not booting, console blank.
Boards boot with flash_linux_m4 target and sampel app rinning from internal M4 sram area.
If any help, thanks !
i am working on both B0 and C0, always using flash_linux_m4_ddr
At now, on B0, cannot see application at 0x88000000 running. I am supposing scm fw is properly initializing ddr. Also since u-boot will run later. But once prepared the container with ddr appliciation, system does not boot.
i am not back working on b0
seco fw is correct : mx8qxb0-ahab-container.img
If i use target flash_linux_m4_ddr with an m4 application built for ddr (0x88000000) ststem resets continuosly, no chars on both m4 / linux console.
If i remove ddr m4 image, system hangs, no charts on console.
If i roll back to flash_linux_m4 target, all works.
well, i rebuilt scm fw with monitor enable (always using flash_linux_m4_ddr target),
and a simple m4 app built to run at 0x88000000.
As said, boards resets but now i can see why:
Hello from SCU (Build 5222, Commit bc122ee1, May 27 2021 16:21:58)
SCFW: DDR frequency = 1200000000
board_set_voltage(A35, 1100, 0)
Start PMIC init
Finished PMIC init
board_set_power_mode(A35, 0, 0, 3)
ROM boot time = 212060 usec
Boot time = 51032 usec
Banner = 8 usec
Init = 10342 usec
Config = 2722 usec
DDR = 10730 usec
SConfig = 5259 usec
Prep = 15064 usec
*** Debug Monitor ***
>$ ipc_err: bad size (0)
ipc_err: bad size (0)
.. reset here
I may be totally wrong, otherwise, please confirm my assumption.
m4 app cannot be run from initial container from ddr @ 0x88000000 (no bootaux, but using flash_linux_m4_ddr) for b0 revision, only app built for tcm seems able to run.
For the following reasons:
- scfw shows BOARD_CPU_RESET_MEM_ERR produced from m4
- m4 app seems to run in parallel to scfw, so probably starts when ddr is still not initialized
- same m4 app works from u-boot bootaux @0x88000000 (ddr properly initialized before)
- C0 revision uses DCD run from ROM bootloader, so ddr4 init at ROM stage allows m4 app to run properly from lpddr4.
Are the above assumptions correct ?
finally i can close this thread.
Non working app on B0 from ddr was due to wrong m4 app compilation flags.
SDK demo apps are using the correct flags.
I can have m4 app working now from both TCM or DDR, on both B0 and C0.