Hi NXP,
There are A53 and M7 in iMX8M plus EVK and I wish I can establish a data link between A53 and M7 to keep them sync data (maybe just simple echo or ping-pong). Once the data sync is missing over timeout time, I can make M7 trigger watchdog to reset A53 and itself.
I download M7 SDK from https://mcuxpresso.nxp.com/en/select and verify the watchdog example.
There are some problems:
1. M7 can trigger watchdog to reset itself, but A53 halt when M7 trigger watchdog
2. Once A53 halt, M7 trigger watchdog again, and M7 halt
3. M7 can not free run. There's no debug message output by M7.
To test and verify:
M7: wdog example (SDK_2_10_0_EVK-MIMX8MP\boards\evkmimx8mp\driver_examples\wdog)
A53: run a simple script to show the date and time every two seconds to confirm if it is working
1. M7 can trigger the first watchdog to reset itself, but A53 halt when M7 triggered the first watchdog.
Then M7 triggers the second watchdog and halt.
2. Modify watchdog example to ignore the first trigger software reset testing.
No matter it starts from power on reset or software reset, it will run watchdog timeout reset testing
When M7 watchdog timeout and trigger reset, A53 still halt
3. Remove segger j-link debugger, turn off power and turn on to let M7 free run.
There's no debug message output from M7.
I test hello_world example (\SDK_2_10_0_EVK-MIMX8MP\boards\evkmimx8mp\demo_apps\hello_world), and there's no debug message output either.
I also download and debug by IAR and it is OK, but there's no debug message output when free run either.
Sophie
M7 can trigger watchdog to reset itself, but A53 halt when M7 trigger watchdog
I'm hitting the same issue on imx8mp evk (MIMX8ML8), even though WDOG3_RST_OPTION and WDOT3_RST_OPTION_M7 of SRC_M7RCR (3039_000C) have been set to 0. We need the wdog to reset the M core only. Please note that this works on imx8mm evk (MIMX8MM6).
I have tried all 4 combinations of 00,01,10,11, none of them fixes the issue.
Could anyone provide some advice?
Hi Igor,
In IMX8MPRM.pdf (i.MX 8M Plus Applications Processor Reference Manual)
Chapter 6.6 Watchdog Timer (WDOG)
I don't quite understand this description.
Will A53 custom timeout watchdog trigger WDOG_B to reset pmic to reset both A53 and M7?
User can custom watchdog timer 0.5 ~ 128 secs, which will trigger WDOG_RESET_B_DEB.
What happen when WDOG_RESET_B_DEB triggered?
What reset fixed 16 secs power down counter to prevent it trigger WDOG_B to reset pmic?
Can M7 trigger WDOG_B, too?
If yes, M7 can do what I want it to do.
Besides, is this resetting flow correct?
M7 watchdog timeout -> A53 halt -> A53 watchdog timeout -> reset pmic -> reset both A53 and M7.
Sophie
