iMX8 SAI I2S clock for 44100,88200.. rates

cancel
Showing results for 
Search instead for 
Did you mean: 

iMX8 SAI I2S clock for 44100,88200.. rates

340 Views
edwardtyrrell
Senior Contributor I

Hi,

Using the iMX8MM-EVK I can play 48K based audio rates (96K, 192K etc) no problem using the built in WM8524 driver and on board codec but after much effort I still cannot play any 44100 based samples (88200, 176400 etc). By what I understand the dai_sysclk used in the function wm8523_set_dai_sysclk() gets it's clock value from the sai1{} in the device tree -> assigned-clock-rates = <24576000>;  Once it has the clock it works out all the divisible rates.

Providng this dtb assigned-clock-rate is divisible by 48000 it works fine. If I try an assigned-clock-rate divisible by 44100 the driver fails and the dai_sysclk value in wm8523_set_dai_sysclk() turns into some wierd value.

How is it possible to get 44100 based rates working with this driver or through a SAI port in general? Then the second question would be how to achieve both 44K1 and 48K rates like in a normal audio card?

Thanks.     

0 Kudos
8 Replies

320 Views
b45499
NXP TechSupport
NXP TechSupport

The default use in the EVK board is WM8524, you can refer to it.

0 Kudos

315 Views
edwardtyrrell
Senior Contributor I

Hi b45499,

Thanks for your reply. That is what we have referred too (please check original post)! We have managed to get 44100 based rates out of the card using the clock configuration below using PLL2 as other forums suggested.

https://community-nxp-com.translate.goog/t5/i-MX-Processors/configure-SAI3-output-clock-frequency-in... 

// 44Ki based rates

// assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
// assigned-clock-rates = <22579200>; 

48K based rates
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
 

However, this product is going to a high-end audio streamer so both 48K and 44K1 rates up are required, how can I get both clocks into our driver? It looks like the iMX8 cannot do this.. This is the most important question to answer now.

Thanks.

0 Kudos

313 Views
b45499
NXP TechSupport
NXP TechSupport

Could you tell us which version BSP are you using?

0 Kudos

309 Views
edwardtyrrell
Senior Contributor I

Hi b45499,

We're using Yocto Honister 5.15.5. Examining the driver code my concern is the driver only excepts one parent clock from the device tree, then using that clock it checks the possible divisions for the audio rates (see wm8524_set_dai_sysclk()). Our product must render native rates without dmix, plughw or any other rate converters. When the PCM is feed 44100, 48000, 176400 or 192000 it must play these rates with no conversion. So, we are halfway there, we can play 44100, 88200, 176400 using PLL2 (SAI1) in the device tree or 44000, 96000, 192000 using PLL1 (SAI1) but never all the rates without changes..

 

Thanks.   

 

Tags (1)
0 Kudos

306 Views
b45499
NXP TechSupport
NXP TechSupport

Dear @edwardtyrrell The result in your side it right, when you need the 48K you need to use the PLL1, and when you use 44.1K you need the PLL2.

0 Kudos

304 Views
edwardtyrrell
Senior Contributor I

Hi b45499,

Yes agree, but we need both audio rates so the codec will render everything; our customers are wanting to play any rate they desire.. Are there any modifications that can be done to the driver to take both PLL1 and PLL2 clocks? If this is not possible then we may have to reconsider the entire SPDIF side of the project. 

Thanks.

0 Kudos

292 Views
b45499
NXP TechSupport
NXP TechSupport

I think both and not realize at the same time, when you need the 48K you need to use the PLL1, and when you use 44.1K you need the PLL2.

0 Kudos

277 Views
edwardtyrrell
Senior Contributor I

Hi, 

That is correct and I fully understand that, however we need a driver that can support all rates. The driver on start-up uses the hard-coded device tree PLL clock and an internal ratio array to work out the rates in which it can support and ALSA can later use; if you supply only the one clock then you will only get one set of rates i.e. all 48K based or the other.  Using the current driver and device tree setup there is only provision to pass in one clock. At start-up the driver needs to see both PLL1 and PLL2 to calculate all the necessary ratios or is it possible to software switch PLL clocks inside the driver and override the PLL selection device tree? 
 

 

0 Kudos