Hi Rogers
please check imx6ull-14x14-ddr3-arm2-cs42888.dts
linux-imx.git - i.MX Linux Kernel
linux-imx.git - i.MX Linux Kernel
AM1848 ESAI
http://www.nxp.com/docs/en/application-note/AN1848.pdf
Best regards
igor
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Igor,
Thank you for your response, but I've been studying that application note(AN1848) for a few days.
I still don't understand how the iMX6ULL ESAI pins map to I2S pins.
AN1848 Table 1-2 describes the following ESAI pins:
SCKR, FSR, HCKR, SCKT, FST, HCKT, SDO5/SDI0, SDO4/SDI1, SDO3/SDI2, SDO1, SDO0.
The iMX6ULL datasheet doesn't reference the names of the ESAI pins.
The Pins for i.MX software names the following ESAI pins:
RX_CLK, RX_FS, RX_HF_CLK, TX0, TX1, TX2_RX3, TX3_RX2, TX4_RX1, TX5_RX0, TX_CLK, TX_FS, HF_CLK
I2S is commonly: DataOut, DataIn, BitCLK, FrameCLK, MasterCLK
The MAX98357 only uses: BitCLK, FrameCLK, and DataIN
On the iMX6ULL ESAI interface, which pins should be connected to BitCLK, FrameCLK, and DataIN?
Best regards,
Rogers
Igor,
I may have just figured it out:
BitCLK = HF_CLK
FrameCLK = TX_FS
DataIN = TX0
Is that correct?
Best regards,
Rogers
Hi Rogers
from linux-imx.git - i.MX Linux Kernel
pinctrl_esai: esaigrp { fsl,pins = < MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0 MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0 MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0 MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0 MX6UL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0 MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0 MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0 MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0 MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0 MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0 MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0 MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0 >; };
also please check sect.4.3 I2S, LEFT-JUSTIFIED, AND EIAJ (RIGHT JUSTIFIED) FORMATS AN1848
Best regards
igor
Igor,
I appreciate your help, but I'm a hardware engineer trying to figure out which pins to connect the on iMX6 to the MAX98357. I do not understand that code.
My problem is the naming convention from the app note doesn't match the pin names found elsewhere.
I think frame sync is D4 and the data outs are D1, F3, E5, F5, F2, D2. But, which is the bit clock? Pin D3 or E4?
Best regards,
Rogers
Hi Rogers
please look at Table 3. ESAI PINMUX AN5350 i.MX 6ULL Migration Guide
http://www.nxp.com/docs/en/application-note/AN5350.pdf
Best regards
igor
Igor,
Thanks for your help.
After I test my board, I'll update this thread.
Best regards,
Rogers