iMX6DL : DDR3 CLK successive output

[koichisakagami]

Dear community,

We investigate a DDR3 clock quality for JEDEC clock jitter test.
We need to output the DDR3 clock continuously .

We executed the " mtest command " on uboot.
However the clock became the intermittent output.

Question.
What kind of method can we output the DDR3 clock in continuously ?

Best Regards,
Koichi Sakagami

[Yuri · Accepted solution]

Hello,

  The i.MX6 MMDC provides clock for DRAM parts, and  - I am afraid -

this is impossible to configure clock generation logic in order to get
continuous  or burst clocks. Basically, clocks are started as soon as

a DRAM chip select is enabled.

  Please try using Stress DDR tool.

https://community.freescale.com/docs/DOC-96412

https://community.freescale.com/docs/DOC-105652

Have a great day,
Yuri

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