iMX6 ULL Error: failed during write leveling calibration

[jeroenvanandel]

On our custom iMX6 ULL design the DDR calibration fails while the DDR stress test 3.0.0 is running without any problems (964 iterations so for) also when the DRAM frequency is set to 450MHz.

Board configuration: 

iMX6 ULL 

DDR3L: MT41K128M16JT-125:K 

DDR Stress Test (3.0.0)

results from DDR Stress Test tool:

Start write leveling calibration...
running Write level HW calibration
  MPWLHWERR register read out for factory diagnostics:
  MPWLHWERR PHY0 = 0x00000000

HW WL cal status: no suitable delay value found for byte 0

HW WL cal status: no suitable delay value found for byte 1

Write leveling calibration completed but failed, the following results were found:
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F

Write DQS delay result:
   Write DQS0 delay: 31/256 CK
   Write DQS1 delay: 31/256 CK

Error: failed during write leveling calibration

[Danube]

Hi Sir,

i.MX6ULL DRAM clock is run 396MHz.

You can set 396MHZ in DDR stress tool.

[jeroenvanandel]

Hi,

I tried calibration both at 400 and 396Mhz but still failing.

I also tried version 2.6.0 of the ddr_stress_tester tool and with this version the Write level HW calibration passes (and also the remaining calibration)

no problems are seen when running the memory  test of the ddr_stress_tester (without doing the calibration)