Hi,
I have a custom board with NXP iMX1176 chip, using the following code ;
#define buffersize (1U*1024U*1024U)
volatile uint32_t test_buf[buffersize];
bool x = false;
while (1) {
for (uint32_t i = 0; i < buffersize; i++) {
test_buf[i] = i;
}
for (uint32_t i = 0; i < buffersize; i++) {
if (test_buf[i] != i) {
while (1);
}
}
GPIO_PinWrite(BOARD_Audio_RST_GPIO, BOARD_Audio_RST_PIN, x);
x = !x;
}
Pin toggle is 800ms in my custom board;
https://www.digikey.com/en/products/detail/etron-technology-inc/EM63A165BM-5IH/10321539
This is the SDRAM which i am using.
I tested the same function in this evaluation kit ; https://www.nxp.com/design/designs/nxp-edgeready-smart-hmi-solution-based-on-i-mx-rt117h-with-ml-vis...
and getting 60ms pin toggle time ,
i have same dcd.c and dcd.h files with eval. board,
for both custom board and eval board SDRAM clocks are same = 200MHz
you can find my clock configuratios on the below picture;
What is the problem? Why my custom board is too slower than eval kit? More thanks for help fron now on.
Hello @jingpan
The buffer is located in BOARD_SDRAM section as shown below;
I would like to run LVGL so the frame buffer should be located here. The capacity of ITCM is not sufficient. I have made the same test on the eval kit speed is 12-13 time better. What could be problem for my custom board?
Hi again @jingpan ,
In our custom boards we have following components;
SDRAM @200MHz;SDRAM which we are using in the custom board
MCU : MIMXRT117HCVM8A @768 MHz
For evaluation kit you can refer ; NXP Eval Kit
Software is almost same with eval kit , so what is the problem with our custom board?
Hi @MFurkan ,
Maybe the SDRAM is not configured properly. Can you use oscilloscope to measure the SDRAM signal?
Regards,
Jing
Hi @jingpan
I measured both custom board and eval kit SDRAMs with oscilloscope you can see the results on the below;
194MHz custom board
200MHz eval kit
Note:My oscilloscope is capable to measure 100MHz signals.
Do you have any suggestion to measure any other signal(s)?
Hi @MFurkan ,
Is this SEMC_CLK? What's the DQS signal look like? It represent read sequence and speed.
Regards,
Jing
Hello again @jingpan
This is our custom boards DQS signal look like shown below;
Best Regards,
Furkan
Hi @MFurkan ,
Please enlarge the time window, I need more signal in a screen. Please also add SEMC_CLK signal to another channel.
The interleave of the two DQS is 200ns. So the max speed is 5M word or 20M byte. Please refer to figure 29-12 in reference manual.
Regards,
Jing
Hi @MFurkan ,
It looks like there is 4 continue DQS in a read sequence. As I analyze in last reply, it is about 20*4=80M, not too bad. If the burst length is 8, it can be even better.
Maybe there is other problem in your code?
Regards,
Jing
Hi @MFurkan ,
Where is this test code? You can put this code in ITCM. This can speed up read/write speed.
This is our test report.
Write is far more faster than read. It's because write operation is pipelined, but read operation must wait till SDRAM feedback.
Regards,
Jing