i.mx7+PF3000: pin config and power domain for eMMC+NAND

[demoniacmilk]

Hello!

I'd like to use eMMC and NAND memory on custom hardware based on the MX7D. Unlike the SABRE Board, both memorys shall be accessible at the same time.

NAND is multiplexed to SD3+SAI Pins. Theres no alternative. NVCC_SD3 and NVCC_SAI will be powered by a 1.8V PMIC output + Ferrite.

eMMC will use the SD1 pins. SD1 provides 4 data lines (SD1_DATA0..3) and allows to multiplex another 4 (SD1_DATA4..7) on ECSPI2 pins. ECSPI1 and ..2 share the same power domain and SPI1 is in use @ 3V3. The eMMC supports HS200 and HS400 modes at 1.8V only. As a result, I can either use:

1. 8 Bit bus width @ 3.3V in normal mode
2. 4 Bit bus width @ 1.8V in HS200 mode

I think HS200 on 4 Bit achieves 100 MByte/s data transfer rate while 8 Bit normal mode can reach up to 52 MByte/s?
The eMMC memory provides a Data strobe signal. The i.mx7 does not provide this signal. If I understood correctly it is used in HS400 mode only?

What power rail should be used for the eMMC and NAND pins on the MX7? NAND will be used as the primary boot memory.
The reference design uses the PF3000's NVCC_SD output on SD1 (external SD card), NVCC_3V3 for eMMC, SW2_1V8 for NAND. I wonder if any of the three power rails might be used here (in regard of their specific voltages) or if any specific connections are required to meet startup sequences or any other requirements.

Thank you,
Regards,
Lars

[Yuri]

Hello,

Please look at my comments below.

1.

  According to the i.MX7 Datasheet it supports 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards

up to 200 MHz in both SDR and DDR modes, includingHS200 and HS400 DDR modes. JEDEC introduced the

following new speed interfaces:

• HS200 starting from JEDEC 4.51: High-speed interface timing, up to 200 MHz single data   rate bus (up to 200 MB/s)

• HS400 starting from JEDEC 5.0: High speed-interface timing, up to 200 MHz dual date  rate bus (up to 400 MB/s)

2.

  From eMMC5.0 spec:

Data Strobe: This signal is generated by the device and used for data output and CRC status response output in HS400 mode. The frequency of this signal follows the frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on the data - one bit for positive edge and the other bit for negative edge. For CRC status response output, the CRC status is latched on the positive edge only, and don't care on the negative edge.

  Basically this signal may left float on the EMMC.

3.

  Customers can follow i.MX7 reference design regarding power supply. I.MX7 power up sequence includes the following restriction regarding the mentioned voltages: all I/O power (NVCC_*) should be turned on after VDD_SVNS_IN is active.

Have a great day,

Yuri

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