i.MX8MM RMII reference clock

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i.MX8MM RMII reference clock

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Sasamy
Contributor IV

Hello, NXP team.

We have a custom board based on i.MX8MM, ethernet PHY LAN8720 with RMII connected as on imx8mm_val (TARGET_IMX8MM_DDR3L_VAL)

https://source.codeaurora.org/external/imx/uboot-imx/tree/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts?h=im...

  pinctrl_fec1: fec1grp {
   fsl,pins = <
    MX8MM_IOMUXC_ENET_MDC_ENET1_MDC  0x3
    MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
    MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
    MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
    MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
    MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56
    MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56
    MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56
    MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
    MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
   >;
  };

RMII reference clock initialization is also similar to this board

https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8mm_val/imx8mm_val.c?h=...

static int setup_fec(void)
{
 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
 /*
 * GPR1 bit 13:
 * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also;
 * 0:enet1 rmii clock comes from external phy or osc
 */

 setbits_le32(&iomuxc_gpr_regs->gpr[1],
   IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT);
 return set_clk_enet(ENET_50MHZ);
}

but the reference clock 50 MHz on the pin MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK is missing.
I checked the integrity of the circuit by configuring this pin as a gpio output. Therefore, I have two questions:

1 Can anyone confirm that such clocking of the RMII works on i.MX8MM?
2 In which version of u-boot it is known that this clocking scheme works?

Alexander

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Alexander

RMII works on i.MX8MM using

imx8mm_val.c\imx8mm_val\freescale\board - uboot-imx - i.MX U-Boot 

One can try to check define "CONFIG_TARGET_IMX8MM_DDR3L_VAL" 

and CCM_CCGR10, for debugging one can use CCM_CLKO1,2 signal clocks,

referencing to Table 5-1. Clock Root Table, sect.5.1.8.38 PLL

Clock Output for Test Enable and Select Register (CCM_ANALOG_ANAMIX_PLL_MNIT_CTL)

Reference Manual, IOMUXC_GPR_GPR1 register

imx8mm_val.h\configs\include - uboot-imx - i.MX U-Boot 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Alexander

RMII works on i.MX8MM using

imx8mm_val.c\imx8mm_val\freescale\board - uboot-imx - i.MX U-Boot 

One can try to check define "CONFIG_TARGET_IMX8MM_DDR3L_VAL" 

and CCM_CCGR10, for debugging one can use CCM_CLKO1,2 signal clocks,

referencing to Table 5-1. Clock Root Table, sect.5.1.8.38 PLL

Clock Output for Test Enable and Select Register (CCM_ANALOG_ANAMIX_PLL_MNIT_CTL)

Reference Manual, IOMUXC_GPR_GPR1 register

imx8mm_val.h\configs\include - uboot-imx - i.MX U-Boot 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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mirceaciocan
Contributor II

Hello, we have the same PHY, the same software and the same issue. The phy is supposedly feed by the ENET1 50MHz clock via ENET_TD2 pad, in our situation the clock is present at the MCU pad, but the frequency is 125MHz !!!, like the RGMII. Of course the config parameters are set to RMII and also to DDR3. Needless to say that the PHY is not exceedingly happy :(.

Also on the NXP DDR3L validation board schematic, a Realtek PHY is used, that has its own oscillator actually generates the clock in the direction of the MCU (external clock situation).

So my question is, is it possible to generate a 50MHz clock from the MCU to the PHY, I know that vice-versa is possible, but I didn't find a way to change the output frequency of the clock, only on how to enable or disable it in different modes via the CCM_CCGR10.

In the data sheet it says it's possible, but no example is given in the Reference Manual or anywhere else that I could find:

Used as RMII clock and RGMII data, there are two RGMII clock schemes.
• MAC generate output 50M reference clock for PHY, and MAC also use this 50M clock.
• MAC use external 50M clock.

Could you please tell me how to actually do it that the output frequency is 50MHz ?

Many thanks for your support,

Mircea

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kl4m4
Contributor II

Same SOC here, different PHY (KSZ8081RNB). Cannot get RMII output 50MHz clock to PHY. When I manually set bit13 in IOMUXC_GPR_GPR1:

devmem2 0x30340004 word 0x2000

I get a clock on PAD_ENET_TD2, but instead of 50MHz, I get 125MHz.

Accepted solution in this thread involves fiddling with u-boot source code. I do not need ethernet during u-boot. Is there a way to fix this just in device tree? So far what I got:

fec1: ethernet@30be0000 { 
compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>,
<&clk IMX8MM_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>,
<&clk IMX8MM_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_125M>,
<&clk IMX8MM_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <0>10m, <125000000>, <50000000>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
nvmem_macaddr_swap;
stop-mode = <&gpr 0x10 3>;
fsl,wakeup_irq = <2>;
status = "disabled";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii"; /* KSZ8081RNB works in RMII mode */
phy-handle = <&ethphy0>;
phy-reset-gpios = <&gpio1 0 0>; /* GPIO1_0 */
fsl,magic-packet;
max-speed = <100>;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};   

Where should I look next?

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Jamier
Contributor II

Did you resolve this. I too see 125MHz instead of the expected 50MHz

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Sasamy
Contributor IV

Hi Igor.

Thanks for the confirmation. It looks like we missed something when adapting u-boot.

Alexander

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