i.MX6SoloX EIM bus timing parameters

[aivchenko]

I'm using asynchronous mode on the bus. So APR=0, SRD=0

I'm basing my parameters on theFigure 23-4  diagram p.1013 of i.MX6SoloX Processor Reference Mamual, Rev.2 9/2017

My EIM CLK is 99MHz

I'm setting RWSC to 10, RCSA=1, RADVA=1 RADVN=1, RCSN=1, OEN=1, WCSA=1, WEA=1, WADVA=1, BEA=1, WADVN=1, WCSN=1, WEN=1, BEN=1

I expect a waveform with CS and OE asserted one clock after read start and lasting 8 clock cycles.

While the timing looks acceptable to me my problem is that CPU inserts long (160ns) delays between read cycles. The code to read the bus is straightforward and contains of four consecutive reads from a bus address (CS2)

        *(u32*)val = *(u32*)0x54000000;
        *(u32*) val= *(u32*)0x54000004;

        *(u32*)val = *(u32*)0x54000000;
        *(u32*)val = *(u32*)0x54000004;

Questions:

1. Is RWSC indeed a time of the whole read cycle (and WWSC for write cycle)?

What I need is /CS2 and /OE (or /WE) to get asserted at the beginning of a read/write cycle and then released one EIM clock before the next cycle.

Are there any CPU limitations for the minimal time between back-to-back transactions on EIM bus?

Thanks

[art]

Q. Is RWSC indeed a time of the whole read cycle (and WWSC for write cycle)?

A. Yes, RWSC indicates the length (in EIM clock cycle units) of the whole read cycle (and WWSC is the same for write cycle).

Q. What I need is /CS2 and /OE (or /WE) to get asserted at the beginning of a read/write cycle.

A. If you need /CS, /OE and /WE to be asserted at the very beginning of a cycle, you have to set RCSA, WCSA, OEA and WEA to 0.

Q. Are there any CPU limitations for the minimal time between back-to-back transactions on EIM bus?

A. Some delays can be added by internal buses arbitration process. These delays are random and not well-predictable.

Also, please check the value of the EIM_CSxGCR1[CSREC] field since it inserts additional delay between back to back bus accesses.

Have a great day,
Artur

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