i.MX6SX can not get into the steady link state with x86

[袁增兴]

Greetings,

Hereafter we ourself are debugging the issues about pcie between imx6sx and x86, after configuring the pcie clock, device type(EP mode) and inbound in imx6sx, data can be accessed into imx6sx from x86, however, it is extremely not stable. Sometimes the data can be written into the ddr of imx6sx from x86, sometimes NOT. Is there anybody run into this problem?

I have written the command to check the PCIE_PHY_DEBUG_R1 register, find that the pcie link state is changing over time, sometime it is in link up state, sometime it is link down or in training state with x86.

Thanks

[袁增兴]

Hi,

We have forced x86 to Gen 1 in BIOS, imx6sx's link state is still not stable.

The de-emphasis value with regard to GPR8 register in u-boot and kernel is different,

The code in u-boot below, 

writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
      (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
      (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
      (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
      (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
      &iomuxc_regs->gpr[8]);

and the code in kernel,

regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
      IMX6Q_GPR8_TX_DEEMPH_GEN1, 20 << 0);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
      IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 20 << 6);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
      IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
      IMX6Q_GPR8_TX_SWING_FULL, 115 << 18);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
      IMX6Q_GPR8_TX_SWING_LOW, 115 << 25);

The two different configuration for gpr8 has no impact on the link state, which is still NOT stable.

[paolo_minazzi]

I see exactly the same problem.

I have :

• a x86 that is PCIe RC
• a iMX6SX that is a PCIe EP

I have tried two x86 modules :

1. an x86 J1900. On this system the PCIe link is stable.
2. an x86 i3. On this system the PCIe link is not stable.

Tried to force Gen1 on both iMX6SX and x86 (BIOS) side.

Tried to change the signal shapes.

Studying the PCIE_PHY_DEBUG_R1:

• on both i3 and J1900 the link bit is on.
• on the i3 the LINK_TRAINING bit continues to toggle.
• on the J1900 the LINK_TRAINING bit is off.

After some minutes on i3 the link goes off.

Have you got an advice ?

Best regards,

Paolo

[igorpadykov]

Hi

issue may be caused by weak/noise signals so may be recommended

to use short cable and try use gen1 mode:

How to force iMX6 PCIe into Gen 1 mode 

Signal shape can be adjusted with IOMUXC_GPR8 please check AN4784

PCIe Certification Guide

http://cache.freescale.com/files/32bit/doc/app_note/AN4784.pdf 

Best regards
igor
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