i.MX6Q: Re-establishing a PCIe link

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i.MX6Q: Re-establishing a PCIe link

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kitz36
Contributor III

Has anyone attempted to re-establish a PCIe link to an endpoint after the link dropped?  In my case I have a Gen2 PCIe link established to a single endpoint when Linux comes up.  I take the endpoint down either by resetting it or performing a PCIe "hot reset".  In all cases the PCIe link comes back as a Gen1 link.  However, as soon as any traffic is sent over the link (reading the Vendor ID via a config-read, for example) the i.MX6Q hangs.

The LTSSM on the i.MX6Q seems to get to the final "L0" state.  I've looked at the link re-establishment using a PCIe protocol analyzer.  I don't think the i.MX6Q ever initiates a "speed change" to Gen2 the way it does on the initial bring-up.

Anyone else see this?

-Charlie

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kitz36
Contributor III

Re-establish a PCIe link is apparently hindered by a published i.MX6 erratum - ERR005184: "PCIe: Clock pointers can lose sync during clock rate changes".  This probably may have been exacerbated in my case since I'm using an external reference for PCIe (see my previous post).  The erratum write up says the workaround is implemented in version ER3 of Freescale's BSP.  However, I think that implementation is incomplete.  The steps that I took to get the link up after it dropped are below.

  1. Disable the LTSSM -- IOMUX GPR12, bit 10 = 0
  2. Reprogram any PCIe PHY registers that were previously overridden.
    1. PCIe PHY registers appear to revert to their reset states when the link goes down (perhaps an errata in of itself?)
    2. Necessary in my case since I'm using an external reference for the PCIe
    3. May be necessary if receiver equalizer settings are adjusted (reference IMX6 erratum ERR004489: "PCIe: 9000505660—PCIe2 receiver equalizer settings").
  3. Disable Gen2 support in the PCIe MAC -- PCIE_RC_LCR, bits [3:0] = 0b0001
  4. Enable the LTSSM -- IOMUX GPR12, bit 10 = 1
  5. Wait for LTSSM to achieve state 17 (L0)  -- call imx_pcie_link_up() routine from the BSP PCIe driver.
  6. Enable Gen2 support in the PCIe MAC -- PCIE_RC_LCR, bits [3:0] = 0b0010
  7. Request a directed speed change to Gen2 -- PCIE_PL_G2CR, bit 17 = 1
  8. Wait for LTSSM to achieve state 17 (L0)

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1,063 Views
kitz36
Contributor III

Re-establish a PCIe link is apparently hindered by a published i.MX6 erratum - ERR005184: "PCIe: Clock pointers can lose sync during clock rate changes".  This probably may have been exacerbated in my case since I'm using an external reference for PCIe (see my previous post).  The erratum write up says the workaround is implemented in version ER3 of Freescale's BSP.  However, I think that implementation is incomplete.  The steps that I took to get the link up after it dropped are below.

  1. Disable the LTSSM -- IOMUX GPR12, bit 10 = 0
  2. Reprogram any PCIe PHY registers that were previously overridden.
    1. PCIe PHY registers appear to revert to their reset states when the link goes down (perhaps an errata in of itself?)
    2. Necessary in my case since I'm using an external reference for the PCIe
    3. May be necessary if receiver equalizer settings are adjusted (reference IMX6 erratum ERR004489: "PCIe: 9000505660—PCIe2 receiver equalizer settings").
  3. Disable Gen2 support in the PCIe MAC -- PCIE_RC_LCR, bits [3:0] = 0b0001
  4. Enable the LTSSM -- IOMUX GPR12, bit 10 = 1
  5. Wait for LTSSM to achieve state 17 (L0)  -- call imx_pcie_link_up() routine from the BSP PCIe driver.
  6. Enable Gen2 support in the PCIe MAC -- PCIE_RC_LCR, bits [3:0] = 0b0010
  7. Request a directed speed change to Gen2 -- PCIE_PL_G2CR, bit 17 = 1
  8. Wait for LTSSM to achieve state 17 (L0)
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