Hi,
I'm trying to enumerate MIPI camera with VC 0 in IMX6 QP SOM, by default I can able to get stream in VC 1. But if I tried to change the VC 0, CSI ID & IPU ID as 0, I'm getting mxc_v4l2_dqueue error
dtb changes:
&mipi_csi {
status = "okay";
ipu_id = <0>;
csi_id = <0>;
v_channel = <0>;
lanes = <2>;
};
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -285,6 +285,7 @@ static void __init imx6q_csi_mux_init(void)
pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",
__func__);
}
+ regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x00);
}
As per IMX6 reference manual, MIPI/CSI2 as VC0 or VC1 should work.
Do I miss any configuration?
Kindly guide to solve this issue.
Please check the register IOMUXC_GPR1[MIPI_IPU1_MUX]. For details, please read the i.MX6Q RM about the IOMUXC_GPR1.