i.MX6 EIM Asynchronous Timing

[mlu]

I am trying to program EIM CS0 for non-multiplexed asynchronous access to CPLD-based registers, but I cannot program proper timing of CS, OE, ADV, etc unless I understand when the processor samples data from the data bus during a read cycle.  I have read the EIM section of the IMX6DQ Reference Manual, but did not find the answer.  When during an asynchronous read cycle does the i.MX6 latch data from the data bus?

[LinWang]

Hi Mike,

Please share your schematic first, let's double check if connections are correct.

Thanks!

Lin