how to use externally generated MCLK with SAI in master mode on i.MX7D?

[rimas]

I am working with the iMX7D SABRE development board and am trying to connect an audio DAC to SAI2 but am confused about how to configure the clocking/pinmux/etc to get the behavior I desire.

I am using an external oscillator to generate the master clock (MCLK) which is connected to the DAC and to an input on the iMX7.  It's not clear to me how to route this MCLK to the SAI2 block.  I want the iMX7D to act as master with respect to the DAC - so the transmit bit clock and frame sync signals are outputs from the iMX7 to the DAC.

What pin(s) on the iMX7 can I use to route this externally generated MCLK to SAI2 and how should I configure the clocking infrastructure (CCM, etc), device tree, and SAI2 control registers to achieve the desired behavior?

Can I use the SAI1_MCLK pad as an input?  Or do I have to use the CCM_EXT_CLK2 clock input, connect this to the AUDIO_PLL in bypass mode and use that as input to SAI2?  Or something else??

I have the SAI control registers set to generate transmit bit clock and frame sync (master mode), but I'm not sure how I should set the MSEL (MCLK select) bits and where to connect the externally generated MCLK.

It is not clear to me from reading the available documentation (chapter 5 and section 13.8 in the iMX7D applications processor reference manual) how to achieve this goal... 

Thanks in advance for any help!!

-Rimas

[igorpadykov]

Hi Rimas

you are right that one can use the CCM_EXT_CLK2 clock input, connecting AUDIO_PLL in bypass
mode and use that as input to SAI2, SAI1_MCLK pad can not be used as input. In i.MX7D MSEL
(MCLK select) has only one option, there are no ways to select others.

Unfortunately I am not aware of additional documenatation except Reference Manual, below links may be helpful

https://community.nxp.com/thread/462742 

I2S1 Slave configuration on iMX7D 

Best regards
igor
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[kwelsh]

igorpadykov‌ You said:

"SAI1_MCLK pad can not be used as input."

Can SAI2_MCLK or SAI3_MCLK be used as inputs? The Reference Manual states:

>> Audio Master Clock. The master clock is an input when externally generated and an output when internally generated.

Is the manual wrong?

[igorpadykov]

>Can SAI2_MCLK or SAI3_MCLK be used as inputs?

I checked internally, from my findings it can not.

In i.MX7D MSEL (MCLK select) has only one option, there are no ways to select others.

In general it can be input with other MSEL settings.

Best regards
igor

[rimas]

Hi Igor,

Thanks for your help.  I have a few more questions regarding the clocking of the SAI modules I'm hoping you can answer:

1.  What is the difference between the SAI{1,2,3}_CLK_ROOT and AUDIO_MCLK_CLK_ROOT clock signals?  How are they used within the SAI blocks?  I'm guessing that AUDIO_MCLK_CLK_ROOT is shared between the 3 instances of the SAI block, but what exactly is it used for?  What is the relationship between AUDIO_MCLK_CLK_ROOT and SAI{1,2,3}_CLOCK_ROOT?

2.  You wrote that in the i.MX7D there is only one option (so no options?) for MSEL.  In the i.MX7 reference manual, there are two MSEL bits defined and there are 4 values defined for it.  Are you saying that the reference manual is wrong and there is actually only availabe master clock (for all 3 SAI instances)?  If this is true, which clock is used as the master clock and how should the MSEL bits be set?

Thanks in advance,

-Rimas

[igorpadykov]

Hi Rimas

1. for SAI_CLK_ROOT and AUDIO_MCLK_CLK_ROOT clock signals one can look at

sect.Clock Control Module (CCM) i.MX7D Reference Manual

http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf

2. only one MSEL option is supported on i.MX7D, it is used in BSP.

Best regards
igor