how to change pin muxing of pad

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how to change pin muxing of pad

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srinivasaporam
Contributor II

Hi,

We are working on a IMX6 board where we have attached a sensor through SPI to ECSPI2. the chip select ECSPI2_SS1 we have choosen as EIM_LBA as per the reference manual.

This EIM_LBA corresponds to GPIO2_IO27 (GPIO59 ((2-1)*32+27)).  From our application we are making this GPIO59 to high and low but it is not happening.

Where as we have cross checked it with another SPI (ECSPI1 with SS0) where ECSPI1_SS0 is taken as EIM_EB2 whose respective GPIO is GPIO2_IO30.

Hi,

in DTS file which is using imx6q-pinfun.h is defined as :

#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B   0x108 0x41c 0x000 0x0 0x0

#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17   0x108 0x41c 0x000 0x1 0x0

#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1  0x108 0x41c 0x820 0x2 0x0

#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27  0x108 0x41c 0x820 0x2 0x0

#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0

In my dtsi/dts files if i use

MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 then SD4_DAT1 should be linked to PWM3 _OUT

and if i use

MX6QDL_PAD_SD4_DAT1__SD4_DATA1  0x17059 then it should be linked automatically to SD4_DATA1

or do we need to do some setting for linking of SD4_DAT1 (in software perspective)

from IMX6DQ reference manual:

By default mux mode of SD4_DAT1 is set to GPIO (GPIO2_IO29)

What should we do to get SD4_DAT1 to PWM3_OUT

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srinivasaporam
Contributor II

No,

Iam saying when I specify in my DTS file as below:

&iomuxc

{

    pinctrl-names = "default";

    imx6qdl-wandboard

    {

     pwm3 {

        pinctrl_pwm3: pwm3grp {

            fsl,pins = <

                MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1

            >;

        };

    };

};

};

SD4_DAT1 is not linking to PWM3_OUT. If i change period, duty_cycle of PWM3 and when Iam probing at SD4_DAT1 , iam not getting any output. where as when iam making GPIO2_IO09 (GPIO41) high or low then when probing at SD4_DAT1 it is also showing high /low.

I mean to say that even if i change SD4_DAT1__PWM3_OUT it is not changing and indeed it is always linked to GPIO (which is the reset value ) for SD4_DAT1.

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igorpadykov
NXP Employee
NXP Employee

connect jtag and check register value of that pad

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727 Views
srinivasaporam
Contributor II

Hi,

But it is not happening like that, Even if use MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 ,SD4_DAT1 is linking with the GPIO2_IO9 because SD4_DAT1 is MUX pad (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1) reset/default value is GPIO2_IO9 (page No: 2156 of IMX6 Dual/Quad Applictions Processor Reference Manual).

But even if it we define iomux in our dts

&iomuxc

{

    pinctrl-names = "default";

    imx6qdl-wandboard

    {

     pwm3 {

        pinctrl_pwm3: pwm3grp {

            fsl,pins = <

                MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1

            >;

        };

    };

};

};

SD4_DAT1 not linking to the PWM3_OUT. What could the problem????

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igorpadykov
NXP Employee
NXP Employee

>SD4_DAT1 not linking to the PWM3_OUT

why are you speaking about GPIO ?

MX6QDL_PAD_SD4_DAT1__PWM3_OUT - means

PWM3 module output will appear on SD4_DAT1 pad,

not GPIO. For GPIO one needs to use MX6QDL_PAD_SD4_DAT1__GPIO2_IO09

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igorpadykov
NXP Employee
NXP Employee

Hi Srinivasa

you are right:

MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 then SD4_DAT1 will be linked to PWM3 _OUT,

that is PWM3 module output will appear on SD4_DAT1 pad.

MX6QDL_PAD_SD4_DAT1__SD4_DATA1  0x17059 then it will be linked automatically to SD4_DATA1

Best regards

igor

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