What is the function of the snvs_hp_VIO_5 and snvs_hp_VIO_5_CTL signals?

[renedebacker]

snvs_hp_VIO_5 is muxed on pin E5 and snvs_hp_VIO_5_CTL is muxed on pin F5.  I can not find any details on the function of these (2) pins.

[igorpadykov]

Hi Rene

these are tamper pins, description can be found in

Security Reference Manual for the i.MX 6ULL Applications Processor

Best regards
igor
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[renedebacker]

Igor,

We are using the i.MX 6UltraLite – MCIMX6G3CVM05AB.

I looked in the Security Reference Manual for the i.mX 6UltraLite Applications Processor – Rev 0, 04/2016 and I could not find any reference to these pins.

What page or section of the SRM are these pins discussed?

Regards,

Rene

Rene DeBacker

Hardware Engineering

E: rdebacker@futurex.com<mailto:rdebacker@futurex.com>

O: +1 (830) 980-9782 x1377

Enterprise encryption & key management solutions for

securing the world’s most sensitive data.

[igorpadykov]

Hi Rene

references can be found in Table 7-4. SNVS _HP security violation sources,
Security violation input 5, sect.7.9.5 SNVS_HP Security Interrupt Control (HPSICR),
sect.7.9.8 SNVS_HP Security Violation Status (HPSVSR), Security Violation Interrupt 5 Enable

Tamper usage is similar to AN12210 Tampering Application for i.MX7Dsabresd
https://www.nxp.com/docs/en/application-note/AN12210.pdf

Best regards
igor

[renedebacker]

Igor,

Thanks.

Table 7-7 SNVS_LP security violation sources list external tamper pin and external tamper pin 2.

I thought there were (10) external tamper pins which could be configured for active(paired) or passive.

Also, the Wire-Mesh Tamper, does that refer to an on-chip wire mesh?

Are there multiple on-chip wire meshes? There are references to (2) meshes.

Regards,

Rene

Rene DeBacker

Hardware Engineering

E: rdebacker@futurex.com<mailto:rdebacker@futurex.com>

O: +1 (830) 980-9782 x1377

Enterprise encryption & key management solutions for

securing the world’s most sensitive data.

[igorpadykov]

Hi Rene

I sent additional materials via mail.

Best regards
igor