What is current MR11/MR12 content in LPDDR4 DRAM?

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What is current MR11/MR12 content in LPDDR4 DRAM?

327 Views
hermann_ruckerb
Contributor III

Hello,

I have a MCIMX93-EVK for testing with Config Tools v14 and v15.

I would be interested to see MR11 and MR12 content from the DRAM (ODT and Vref settings).

When looking  to Code Preview i see 

ddrparam set MR11 0x46 
ddrparam set MR12 0x11

But i am not sure:

Is this the original config that is used to start the training, or is this the final value after training the system? 

Is there any way to read out the MR during normal operation (e. g. under linux?) 

 

I would be also happy if anybody could tell me, where i find the final Settings for

Soc Drivestrength and Termination... 

Is this training result also listed in the Code preview?

 

thanks a lot

 

Hermann 

 

 

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4 Replies

242 Views
hermann_ruckerb
Contributor III

Hello Jorge,

i have to admit, that i do still do not fully understand the init of .iMX93.

Most of the time i work with x86 controllers that do the full calibration automatically. Calibration includes all Vref, Timing, Write leveleing, Readleveling, Driverstength, Termination optimization..

From i.MX6 i remember this had do be done manually and programmed in the init scripts.

I thought that after i.MX6 nxp also introduced a full training during power up. but it seems i am wrong here. 

For some reasons that i do not want ot share public i am only working with the configtools in the moment, so i am not sure how to deal now with the modification that would be needed.. 

Hermann.

P.S. nxp forum support is really good, but i still do not like this kind of support: It is public and i always need to think about "what information can i share, what not" .. .therefore a public forum support is not really a professional way of support in my opinion.. 

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306 Views
JorgeCas
NXP TechSupport
NXP TechSupport

Hello, I hope you are doing well.

Is this the original config that is used to start the training, or is this the final value after training the system?

It will keep the value what you have set to MR.

Is there any way to read out the MR during normal operation (e. g. under linux?)

Is this training result also listed in the Code preview?

For that I have understood it is not possible to read this registers from user space or U-boot but, maybe you could try to read MR11/MR12 content as is done on ddr_init.c

Best regards.

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264 Views
hermann_ruckerb
Contributor III

Hello, 

i have to admit, that I only do the Measurement .. not the config, 
Usually i work with controllers that do the Training on their own... it looks like for i.MX93 i need to do the characterization and then set the config manually ??? (i thought this was the process for i.MX6 and since that time nxp added an automated training ...) 

But looking to the vTSA results for write this does not look like a result that i would trust:Write_vTSA_DQ0.jpg

so this resutls would indicate to set Vref to 0.1548mV and I would need to set this manually in the Code?

but as the lower level seems to be way to high (79mV) in order to get a reasonable eye the proposed vref seems way too hight. 

for read it looks more reasonable: 

Read_vTSA_DQ0.jpg

I use the imx93-evk eval board and pre-configuration in my setup, so i expected all settings correct and i did not change these.

But based on these results i would expect i need to adjust the configuration for the settings for this board? 

Sorry for this stupid question:
So my assumption is, that i need to go into the Registers tab, find e. g.the Register for SoC drive strength, DRAM termination, modify this, download this and re-do the vTSA to find the result for the new setting, then modify Vref to the reported value from vTSA and enter this in the Registers tab again.
Is this the expected process? 

I was looking to find SoC drivestrength register in the RefManual but was not successful .. can you tell me this register? (I hope this register would help to find also the other registers that I am missing )

 Maybe the better way would be to set a different lower limit in the vTSA in order to get a full eye, not jsut the upper half end then get a better result ... 

 

Thanks for any feedback, and sorry again for my stupid questions.. 

 

Hermann 

 

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258 Views
JorgeCas
NXP TechSupport
NXP TechSupport

Hello,

It looks like for i.MX93 i need to do the characterization and then set the config manually ?

No, I think I was not clear.

Usually, MR contents are defined on ddr_config.ds file according to your DDR configuration. The board will perform a calibration and MR content will not change after calibration. You could try to test it to see changes if any.

But based on these results I would expect I need to adjust the configuration for the settings for this board?

No, I think not, because these are the tested settings.

I suggest you enter your DDR configuration to create the initialization scripts and could do a modification if needed.

Best regards.

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