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Using lpuart3 on IMX8QM_ENET1_RGMII pins on i.MX8QM

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Using lpuart3 on IMX8QM_ENET1_RGMII pins on i.MX8QM

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‎06-28-2023 12:15 PM
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Peter_ManyPebbles
Contributor II

Hi, I am working on a Variscite i.MX8QM "Spear" SOM but with a custom carrier PCB.

On the Variscite example board the IMX8QM_ENET1_RGMII pins are used to drive an Eth1 port complimenting the Eth0 port however on our custom carrier PCB we have removed the second Ethernet port (Eth1) in order to access UART3 on the same pins. (Eth0 works well still ).

I have rationalised the DT so although we are using a Variscite SOM, I have cut it back and made comparisons to native NXP DTs so I believe that it is comparable since it shares the same included headers eg to "imx8qm-mek.dts".

The Ethernet 1 port is operational on the Variscite carrier PCB so it can be assumed that the pins are broken out from the SOM accordingly and I should be able as a consequence to access UART3 on these pins.

In my DT, the pin assignments associated with fec2 have been removed and replaced with pin assignments for UART3 on the IMX8QM_ENET1_RGMII pin set in accordance with pads-imx8qm.h but I simply can't get ANYTHING out of UART3.

I have a GPS module that transmits data at 1 second intervals and it works absolutely fine on UART2 but nothing comes through on UART3. I can test the input on the UART RX ports (ttyLP2 or ttyLP3) using either of:

$ cat /dev/ttyLP3

$ picocom -b 9600 -r -l /dev/ttyLP3

This is my DT:

 

/*
 * Copyright 2019 Variscite Ltd.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include "imx8qm.dtsi"

#include <dt-bindings/usb/pd.h>

/ {
	model = "Variscite sen-eld0007-01 i.MX8QM";
	
	compatible = "fsl,imx8qm-var-spear", "fsl,imx8qm";

	chosen {
		stdout-path = &lpuart0;
	};

	aliases {
		gpio0 = &lsio_gpio0;
		gpio1 = &lsio_gpio1;
		gpio2 = &lsio_gpio2;
		gpio3 = &lsio_gpio3;
		gpio4 = &lsio_gpio4;
		gpio5 = &lsio_gpio5;
		gpio6 = &lsio_gpio6;
		gpio7 = &lsio_gpio7;
		i2c0  = &i2c0;
		i2c1  = &i2c1;
		i2c2  = &i2c2;
		i2c3  = &i2c3;
		i2c4  = &i2c4;
	};

	regulators: regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "sw-3p3-sd1";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		hsic_io_power: hsic_io_power {
			compatible = "regulator-fixed";
			regulator-name = "hsic_io_power";
			regulator-always-on;
		};

		hsic_host1_vbus: hsic_host1_vbus {
			compatible = "regulator-fixed";
			regulator-name = "hsic_host1_vbus";
			gpio = <&lsio_gpio1 12 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			regulator-always-on;
		};

		hsic_host2_vbus: hsic_host2_vbus {
			compatible = "regulator-fixed";
			regulator-name = "hsic_host2_vbus";
			gpio = <&lsio_gpio1 16 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			regulator-always-on;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		decoder_boot: decoder_boot@0x84000000 {
			no-map;
			reg = <0 0x84000000 0 0x2000000>;
		};

		decoder_rpc: decoder_rpc@0x92000000 {
			no-map;
			reg = <0 0x92000000 0 0x200000>;
		};

		dsp_reserved: dsp@0x92400000 {
			no-map;
			reg = <0 0x92400000 0 0x2000000>;
		};

		encoder_boot: encoder_boot@0x86000000 {
			no-map;
			reg = <0 0x86000000 0 0x400000>;
		};

		encoder_reserved: encoder_reserved@0x94400000 {
			no-map;
			reg = <0 0x94400000 0 0x800000>;
		};

		encoder_rpc: encoder_rpc@0x92200000 {
			no-map;
			reg = <0 0x92200000 0 0x200000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x3c000000>;
			alloc-ranges = <0 0x96000000 0 0x3c000000>;
			linux,cma-default;
		};

		ts_boot: ts_boot@0x95000000 {
			no-map;
			reg = <0 0x95000000 0 0x400000>;
		};
	};

	sound-wm8904 {
		compatible = "fsl,imx-audio-wm8904";
		model = "imx-wm8904";
		audio-codec = <&wm8904>;
		audio-cpu = <&esai0>;
		status = "disabled";
	};
	
	backlight_lvds0: backlight_lvds@0 {
		compatible = "pwm-backlight";
		pwms = <&pwm_lvds0 0 100000 0>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
		status = "okay";
	};
	
	panel@0 {
		compatible = "sgd,gktw70sdae4se", "panel-lvds";
		backlight = <&backlight_lvds0>;
		width-mm = <153>;
		height-mm = <87>;
		label = "gktw70sdae4se";
		data-mapping = "jeida-24";
		status = "okay";

		panel-timing {
			clock-frequency = <35714000>;
			hactive = <800>;
			vactive = <480>;
			hback-porch = <39>;
			hfront-porch = <39>;
			vback-porch = <29>;
			vfront-porch = <13>;
			hsync-len = <47>;
			vsync-len = <2>;
			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <0>;
		};

		port {
			panel0_in: endpoint {
				remote-endpoint = <&lvds0_out>;
			};
		};
	};
	
	backlight_lvds1: backlight_lvds@1 {
		compatible = "pwm-backlight";
		pwms = <&pwm_lvds1 0 100000 0>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
		status = "disabled";
	};


	panel@1 {
		compatible = "sgd,gktw70sdae4se", "panel-lvds";
		backlight = <&backlight_lvds1>;
		width-mm = <153>;
		height-mm = <87>;
		label = "gktw70sdae4se";
		data-mapping = "jeida-24";
		status = "okay";

		panel-timing {
			clock-frequency = <35714000>;
			hactive = <800>;
			vactive = <480>;
			hback-porch = <39>;
			hfront-porch = <39>;
			vback-porch = <29>;
			vfront-porch = <13>;
			hsync-len = <47>;
			vsync-len = <2>;
			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <0>;
		};

		port {
			panel1_in: endpoint {
				remote-endpoint = <&lvds1_out>;
			};
		};
	};	
};

&acm {
	status = "okay";
};

&asrc0 {
	status = "disabled";
};

&asrc1 {
	status = "disabled";
};

&cm40_intmux {
	status = "okay";
};

&cm41_intmux {
	status = "okay";
};

&dc0_pc {
	status = "okay";
};

&dc1_pc {
	status = "okay";
};

&dc0_prg1 {
	status = "okay";
};

&dc0_prg2 {
	status = "okay";
};

&dc0_prg3 {
	status = "okay";
};

&dc0_prg4 {
	status = "okay";
};

&dc0_prg5 {
	status = "okay";
};

&dc0_prg6 {
	status = "okay";
};

&dc0_prg7 {
	status = "okay";
};

&dc0_prg8 {
	status = "okay";
};

&dc0_prg9 {
	status = "okay";
};

&dc0_dpr1_channel1 {
	status = "okay";
};

&dc0_dpr1_channel2 {
	status = "okay";
};

&dc0_dpr1_channel3 {
	status = "okay";
};

&dc0_dpr2_channel1 {
	status = "okay";
};

&dc0_dpr2_channel2 {
	status = "okay";
};

&dc0_dpr2_channel3 {
	status = "okay";
};

&dpu1 {
	status = "okay";
};

&dc1_prg1 {
	status = "okay";
};

&dc1_prg2 {
	status = "okay";
};

&dc1_prg3 {
	status = "okay";
};

&dc1_prg4 {
	status = "okay";
};

&dc1_prg5 {
	status = "okay";
};

&dc1_prg6 {
	status = "okay";
};

&dc1_prg7 {
	status = "okay";
};

&dc1_prg8 {
	status = "okay";
};

&dc1_prg9 {
	status = "okay";
};

&dc1_dpr1_channel1 {
	status = "okay";
};

&dc1_dpr1_channel2 {
	status = "okay";
};

&dc1_dpr1_channel3 {
	status = "okay";
};

&dc1_dpr2_channel1 {
	status = "okay";
};

&dc1_dpr2_channel2 {
	status = "okay";
};

&dc1_dpr2_channel3 {
	status = "okay";
};

&dpu2 {
	status = "okay";
};

&esai0 {
	status = "disabled";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	fsl,magic-packet;
	phy-reset-gpios = <&lsio_gpio2 28 GPIO_ACTIVE_LOW>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	phy-reset-duration = <10>;
	phy-reset-post-delay = <20>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			at803x,vddio-1p8v;
			at803x,eee-disabled;
			reg = <0>;
		};
	};
};

&fec2 {
	status = "disabled";
};

&flexcan1 {
	status = "disabled";
};

&flexcan2 {
	status = "disabled";
};

&flexcan3 {
	status = "disabled";
};

&flexspi0 {
	status = "disabled";
};

&gpu_3d0 {
	status = "okay";
};

&gpu_3d1 {
	status = "okay";
};

&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";
	
	captouch: ft5x06_ts@38 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_captouch>;
		compatible = "edt,edt-ft5x06";
		reg = <0x38>;
		interrupt-parent = <&lsio_gpio1>;
		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
		reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
		touchscreen-inverted-x;
		touchscreen-inverted-y;
		status = "okay";
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";

	/* USB Type-C Controller */
	typec_ptn5150: typec@3d {
		compatible = "nxp,ptn5150";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ptn5150>;
		reg = <0x3d>;
		int-gpio = <&lsio_gpio0 19 GPIO_ACTIVE_HIGH>;
		status ="okay";
	};
};

&i2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	status = "okay";
	
	usb3503@8 {
		compatible = "smsc,usb3503";
		reg = <0x08>;
		connect-gpios = <&lsio_gpio1 6 GPIO_ACTIVE_LOW>;
		reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>;
		initial-mode = <1>;
	};
	
	/* PCF8523 RTC module */
	pcf8523: rtc@68 {
		compatible = "nxp,pcf8523";
		reg = <0x68>;
		status = "okay";
	};
};

&i2c4 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c4>;
	status = "okay";
	
	wm8904: codec@1a {
		compatible = "wlf,wm8904";
		reg = <0x1a>;
		status = "disabled";
	};
};

&i2c_mipi_csi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
	clock-frequency = <100000>;
	status = "okay";

	imx290_mipi0: imx290_mipi@1a {
		compatible = "sony,imx290-mono";
		reg = <0x1a>;
		
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mipi_csi0>;
		clocks = <&xtal24m>;
		clock-names = "xclk";
		clock-frequency = <37125000>;
		csi_id = <0>;
		powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>;
		mclk = <24000000>;
		mclk_source = <0>;
		mipi_csi;

		status = "okay";
		port {
			imx290_mipi_0_ep: endpoint {
				remote-endpoint = <&mipi_csi0_ep>;
				data-lanes = <1 2 3 4>;
				link-frequencies = /bits/ 64 <148500000 222750000 297000000 445500000>;
				clocks-lanes = <0>;
			};
		};
	};
};

&i2c_mipi_csi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c_mipi_csi1>;
	clock-frequency = <100000>;
	status = "okay";

	arducam_pivariety: arducam_pivariety@c {
		compatible = "arducam,arducam-pivariety";
		reg = <0x0c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mipi_csi1>;
		clocks = <&xtal24m>;
		clock-names = "xclk";
		clock-frequency = <37125000>;
		csi_id = <1>;
		powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>;
		mclk = <24000000>;
		mclk_source = <0>;
		mipi_csi;

		status = "okay";
		port {
			pivariety_mipi_1_ep: endpoint {
				remote-endpoint = <&mipi_csi1_ep>;
				data-lanes = <1 2 3 4>;
				clocks-lanes = <0>;
				link-frequencies = /bits/ 64 <493500000>;
			};
		};
	};
};

&imx8_gpu_ss {
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;
	
	imx8qm_var_spear {
	
		pinctrl_hog: hoggrp {
			fsl,pins = <
				IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14				0x00000041
				IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15			0x00000041
				IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04			0x00000041
				IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05			0x00000041
				IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06			0x00000041
				IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000041
				IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08			0x00000041
				IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09			0x00000041
				IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10			0x00000041
				IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11			0x00000041
				IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12			0x00000041
				IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13			0x00000041
				IMX8QM_SPDIF0_RX_LSIO_GPIO2_IO14			0x00000041
				IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15			0x00000041
				IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16			0x00000041
				IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12				0x00000041
				IMX8QM_SAI1_RXD_LSIO_GPIO3_IO13				0x00000041
				IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14			0x00000041
				IMX8QM_SAI1_TXC_LSIO_GPIO3_IO15				0x00000041
				IMX8QM_SAI1_TXD_LSIO_GPIO3_IO16				0x00000041
				IMX8QM_SAI1_TXFS_LSIO_GPIO3_IO17			0x00000041
				IMX8QM_MLB_SIG_LSIO_GPIO3_IO26				0x00000041
				IMX8QM_MLB_CLK_LSIO_GPIO3_IO27				0x00000041
				IMX8QM_MLB_DATA_LSIO_GPIO3_IO28				0x00000041
				IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31			0x00000041
				IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00			0x00000041
				IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01			0x00000041
				IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15		0x00000041
				IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16		0x00000041
				IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19			0x00000041
				IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20			0x00000041
				IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21			0x00000041
				IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23			0x00000041
			>;
		};


		pinctrl_captouch: captouchgrp {
			fsl,pins = <
				IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11			0x00000021
				IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05			0x00000021
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000048
				IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
				IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
				IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000048
				IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000048
				IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000048
				IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000048
				IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000048
				IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000048
				IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
				IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000048
				IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000048
				IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000048
				IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000048
				IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28			0x06000048
			>;
		};

		pinctrl_hdmi_i2c: hdmii2cgrp {
			fsl,pins = <
				IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27	0x00000021
			>;
		};

		pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 {
			fsl,pins = <
				IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL	0xc2000020
				IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA	0xc2000020
			>;
		};

		pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 {
			fsl,pins = <
				IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL	0xc2000020
				IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA	0xc2000020
			>;
		};

		pinctrl_lpi2c0: lpi2c0grp {
			fsl,pins = <
				IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL		0xc6000020
				IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA		0xc6000020
			>;
		};

		pinctrl_lpi2c1: lpi2c1grp {
			fsl,pins = <
				IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA			0xc6000020
				IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL			0xc6000020
			>;
		};

		pinctrl_lpi2c2: lpi2c2grp {
			fsl,pins = <
				IMX8QM_GPT1_CLK_DMA_I2C2_SCL			0xc6000020
				IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA		0xc6000020
			>;
		};

		pinctrl_lpi2c4: lpi2c4grp {
			fsl,pins = <
				IMX8QM_ENET1_MDC_DMA_I2C4_SCL			0xc6000020
				IMX8QM_ENET1_MDIO_DMA_I2C4_SDA			0xc6000020
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				IMX8QM_UART0_RX_DMA_UART0_RX			0x06000020
				IMX8QM_UART0_TX_DMA_UART0_TX			0x06000020
				IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B		0x06000020
				IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B		0x06000020
				IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02		0x06000020
			>;
		};

		pinctrl_lpuart1: lpuart1grp {
			fsl,pins = <
				IMX8QM_UART1_RX_DMA_UART1_RX			0x06000020
				IMX8QM_UART1_TX_DMA_UART1_TX			0x06000020
				IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B		0x06000020
				IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B		0x06000020
			>;
		};

		pinctrl_lpuart2: lpuart2grp {
			fsl,pins = <
				IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX		0x06000020
				IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX		0x06000020
			>;
		};
		
		pinctrl_lpuart3: lpuart3grp {
			fsl,pins = <
				IMX8QM_ENET1_RGMII_RXD3_DMA_UART3_RX		0x06000020
				IMX8QM_ENET1_RGMII_TXD2_DMA_UART3_TX		0x06000020
				IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B		0x06000020
				IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B		0x06000020
			>;
		};

		pinctrl_lpspi0: lpspi0grp {
			fsl,pins = <
				IMX8QM_SPI0_SCK_DMA_SPI0_SCK			0x0600004c
				IMX8QM_SPI0_SDO_DMA_SPI0_SDO			0x0600004c
				IMX8QM_SPI0_SDI_DMA_SPI0_SDI			0x0600004c
			>;
		};

		pinctrl_lpspi0_cs: lpspics0grp {
			fsl,pins = <
				IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05			0x00000021
				IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06			0x00000021
			>;
		};

		pinctrl_lpspi2: lpspi2grp {
			fsl,pins = <
				IMX8QM_SPI2_SCK_DMA_SPI2_SCK			0x0600004c
				IMX8QM_SPI2_SDO_DMA_SPI2_SDO			0x0600004c
				IMX8QM_SPI2_SDI_DMA_SPI2_SDI			0x0600004c
			>;
		};

		pinctrl_lpspi2_cs: lpspics2grp {
			fsl,pins = <
				IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10			0x00000021
				IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11			0x00000021
			>;
		};

		pinctrl_lpspi3: lpspi3grp {
			fsl,pins = <
				IMX8QM_SPI3_SCK_DMA_SPI3_SCK			0x0600004c
				IMX8QM_SPI3_SDO_DMA_SPI3_SDO			0x0600004c
				IMX8QM_SPI3_SDI_DMA_SPI3_SDI			0x0600004c
			>;
		};

		pinctrl_lpspi3_cs: lpspics3grp {
			fsl,pins = <
				IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20			0x00000021
				IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21			0x00000021
			>;
		};

		pinctrl_mipi_csi0: mipi_csi0 {
			fsl,pins = <
				IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27		0xC0000041
				IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0xC0000041
			>;
		};

		pinctrl_mipi_csi1: mipi_csi1 {
			fsl,pins = <
				IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0xC0000041
				IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31		0xC0000041
			>;
		};

		pinctrl_mlb: mlbgrp {
			fsl,pins = <
				IMX8QM_MLB_SIG_CONN_MLB_SIG			0x00000021
				IMX8QM_MLB_CLK_CONN_MLB_CLK			0x00000021
				IMX8QM_MLB_DATA_CONN_MLB_DATA			0x00000021
			>;
		};

		pinctrl_ptn5150: ptn5150grp {
			fsl,pins = <
				IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19		0x00000021
			>;
		};

		pinctrl_pwm_lvds0: lvds0pwmgrp {
			fsl,pins = <
				IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT		0x00000020
			>;
		};

		pinctrl_pwm_lvds1: lvds1pwmgrp {
			fsl,pins = <
				IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10		0x00000020
			>;
		};

		pinctrl_usbotg1: usbotg1 {
			fsl,pins = <
				IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
				IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
				IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021
				IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021
				IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021
				IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021
				IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021
				IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021
				IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021
				IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021
				IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000041
				IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040
				IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020
				IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000020
				IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000020
				IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000020
				IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000020
				IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000020
				IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000020
				IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000020
				IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000020
				IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040
				IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040
				IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020
				IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000020
				IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000020
				IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000020
				IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000020
				IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000020
				IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000020
				IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000020
				IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000020
				IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040
				IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22		0x00000021
				IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07		0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
				IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
				IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000021
				IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000021
				IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000021
				IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000021
				IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020
				IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020
				IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020
				IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020
				IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020
				IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020
				IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020
				IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020
				IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK		0x06000041
				IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD		0x00000021
				IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021
				IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021
				IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021
				IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
				IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
				IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000020
				IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000020
				IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000020
				IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000020
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
				IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
				IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000020
				IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000020
				IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000020
				IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000020
			>;
		};

		pinctrl_usb_hsic_idle: usbhsic_idle {
			fsl,pins = <
				IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06		0x00000021
				IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07		0x00000021
				IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12		0x00000021
				IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16	0x00000021
				IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA	0xc60000cf
				IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0xc60000cf
			>;
		};

		pinctrl_usb_hsic_active: usbsic_active {
			fsl,pins = <
				IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06		0x00000021
				IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07		0x00000021
				IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12		0x00000021
				IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16	0x00000021
				IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA	0xc60000cf
				IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0xc60000ff
			>;
		};

		pinctrl_wifi: wifigrp {
			fsl,pins = <
				IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0xc600004c /* WIFI_32K_CLK   */
				IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31		0x06000021 /* WIFI_REG_ON    */
				IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30		0x00000021 /* BT_REG_ON      */
				IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26		0x00000021 /* BT_BUF         */
				IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08		0x00000021 /* RS-422 control */
			>;
		};
	};
};

&irqsteer_csi0 {
	status = "okay";
};

&irqsteer_csi1 {
	status = "okay";
};

&isi_0 {
	status = "okay";

	cap_device {
		status = "okay";
	};

	m2m_device {
		status = "disabled";
	};
};

&isi_1 {
	status = "disabled";
};

&isi_2 {
	status = "disabled";
};

&isi_3 {
	status = "disabled";
};

&isi_4 {
	status = "okay";

	cap_device {
		status = "okay";
	};

	m2m_device {
		status = "okay";
	};
};

&isi_5 {
        status = "disabled";
};

&isi_6 {
        status = "disabled";
};

&isi_7 {
        status = "disabled";
};

&jpegdec {
       status = "okay";
};

&jpegenc {
       status = "okay";
};

&lpspi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
	cs-gpios = <&lsio_gpio3 5 0>,
		   <&lsio_gpio3 6 0>;
	status = "okay";

        spidev@0 {
		compatible = "var,spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "okay";
        };

        spidev@1 {
		compatible = "var,spidev";
		spi-max-frequency = <12000000>;
		reg = <1>;
		status = "okay";
        };
};

&lpspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
	cs-gpios = <&lsio_gpio3 10 0>,
		   <&lsio_gpio3 11 0>;
	status = "okay";

        spidev@0 {
		compatible = "var,spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "okay";
	};
		
        spidev@1 {
		compatible = "var,spidev";
		spi-max-frequency = <12000000>;
		reg = <1>;
		status = "okay";
        };
};

&lpspi3 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi3 &pinctrl_lpspi3_cs>;
	cs-gpios = <&lsio_gpio2 20 0>,
		   <&lsio_gpio2 21 0>;
	status = "okay";

        spidev@0 {
		compatible = "var,spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "okay";
	};
	
        spidev@1 {
		compatible = "var,spidev";
		spi-max-frequency = <12000000>;
		reg = <1>;
		status = "okay";
        };
};

&lpuart0 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};


&lpuart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	uart-has-rtscts;
	status = "okay";
};

&lpuart2 { /* Header */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "okay";
};

&lpuart3 { /* GPS */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "okay";
};

&lsio_gpio1 {
	/* Enable wakeup-source from Capacitive touch */

	pad-wakeup-num = <1>;	/* Total number of wakeup pads in gpio1 bank */

	/*
	 IMX8QM_LVDS0_GPIO01:   Touch IRQ pin id
	 SC_PAD_WAKEUP_LOW_LVL: trigger type
	 5:                     Touch IRQ gpio pin
	*/
	pad-wakeup = <IMX8QM_LVDS0_GPIO01 SC_PAD_WAKEUP_LOW_LVL 5>;

	/* From LVDS control: */
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hdmi_i2c>;

        hdmi_i2c_signal_route {
                gpio-hog;
                gpios = <22 GPIO_ACTIVE_HIGH>;
                output-low;
                line-name = "hdmi_i2c";
        };
};

&lsio_gpio5 {
};

&mipi_csi_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	/* Camera 0  MIPI CSI-2 (CSIS0) */
	port@0 {
		reg = <0>;
		mipi_csi0_ep: endpoint {
			remote-endpoint = <&imx290_mipi_0_ep>;
			data-lanes = <1 2 3 4>;
		};
	};
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	/* Camera 1  MIPI CSI-2 (CSIS1) */
	port@1 {
		reg = <1>;
		mipi_csi1_ep: endpoint {
			remote-endpoint = <&pivariety_mipi_1_ep>;
			data-lanes = <1 2 3 4>;
		};
	};
};

&mlb {
	status = "disabled";
};

&mu_m0{
	interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
};

&mu1_m0{
	interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
};

&mu2_m0{
	interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
	status = "okay";
};

&mu3_m0{
	interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
	status = "okay";
};

&pciea {
	status = "disabled";
};

&pcieb {
	status = "disabled";
};

&pwm_lvds0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm_lvds0>;
        status = "okay";
};

&pwm_lvds1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm_lvds1>;
        status = "disabled";
};

/* SOM fake RTC - do not use! */
&rtc {
	status = "disabled";
};

&sai6 {
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "disabled";
};

&sai7 {
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "disabled";
};

&sata{
	status = "disabled";
};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};
			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};
		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
				<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>;
	bus-width = <4>;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

&usbphy1 {
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	srp-disable;
	hnp-disable;
	adp-disable;
	ci-disable-lpm;
	power-active-high;
	disable-over-current;
	status = "okay";
};

&usb3phynop1 {
	status = "okay";
};

&usbotg3 {
	dr_mode = "otg";
	extcon = <&typec_ptn5150>;
	status = "okay";
};

&usbphynop2 {
	status = "okay";
};

&usbh1 {
	pinctrl-names = "idle", "active";
	pinctrl-0 = <&pinctrl_usb_hsic_idle>;
	pinctrl-1 = <&pinctrl_usb_hsic_active>;
	srp-disable;
	hnp-disable;
	adp-disable;
	disable-over-current;

	status = "okay";
};

&vpu_decoder {
	compatible = "nxp,imx8qm-b0-vpudec";
	boot-region = <&decoder_boot>;
	rpc-region = <&decoder_rpc>;
	reg-csr = <0x2d080000>;
	core_type = <2>;
	status = "okay";
};

&vpu_encoder {
	compatible = "nxp,imx8qm-b0-vpuenc";
	boot-region = <&encoder_boot>;
	rpc-region = <&encoder_rpc>;
	reserved-region = <&encoder_reserved>;
	reg-rpc-system = <0x40000000>;
	resolution-max = <1920 1080>;
	power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>,
			<&pd IMX_SC_R_VPU>;
	power-domain-names = "vpuenc1", "vpuenc2", "vpu";
	mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx",
		     "enc2_tx0", "enc2_tx1", "enc2_rx";
	mboxes = <&mu1_m0 0 0
		  &mu1_m0 0 1
		  &mu1_m0 1 0
		  &mu2_m0 0 0
		  &mu2_m0 0 1
		  &mu2_m0 1 0>;
	status = "okay";

	vpu_enc_core0: core0@1020000 {
		compatible = "fsl,imx8-mu1-vpu-m0";
		reg = <0x1020000 0x20000>;
		reg-csr = <0x1090000 0x10000>;
		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
		fsl,vpu_ap_mu_id = <17>;
		fw-buf-size = <0x200000>;
		rpc-buf-size = <0x80000>;
		print-buf-size = <0x80000>;
	};

	vpu_enc_core1: core1@1040000 {
		compatible = "fsl,imx8-mu2-vpu-m0";
		reg = <0x1040000 0x20000>;
		reg-csr = <0x10A0000 0x10000>;
		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
		fsl,vpu_ap_mu_id = <18>;
		fw-buf-size = <0x200000>;
		rpc-buf-size = <0x80000>;
		print-buf-size = <0x80000>;
	};
};

&vpu_ts {
	compatible = "nxp,imx8qm-b0-vpu-ts";
	boot-region = <&ts_boot>;
	reg-csr = <0x2d0b0000>;
	status = "okay";
};

&ldb1 {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		status = "okay";

		port@1 {
			reg = <1>;

			lvds0_out: endpoint {
				remote-endpoint = <&panel0_in>;
			};
		};
	};
};

&ldb1_phy {
	status = "okay";
};

&ldb2 {
	status = "disabled";

	lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		status = "okay";

		port@1 {
			reg = <1>;

			lvds1_out: endpoint {
				remote-endpoint = <&panel1_in>;
			};
		};
	};
};

&ldb2_phy {
	status = "disabled";
};

 

 

I have also tried adding additional features to the DT eg expanding the &lpuart section to read:

 

 

& lpuart3 {   /* GPS */  
	pinctrl-names =   "default"  ;  
	pinctrl-0   =   <  &pinctrl_lpuart3 >  ;  
	power-domains =   <  &pd IMX_SC_R_UART_3 >  ;  
	status =   "okay"  ;  
}  ;

 

 

or:

 

 

&lpuart3 { /* GPS */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gic>;
	clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>;
	clock-names = "ipg", "baud";
	assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
	assigned-clock-rates = <80000000>;
	power-domains = <&pd IMX_SC_R_UART_3>;
	power-domain-names = "uart";
	dma-names = "tx","rx";
	dmas = <&edma2 19 0 0>,
		<&edma2 18 0 1>;
	status = "okay";
};

 

 

and even a power control enable command:

 

 

& uart3_lpcg {  
status =   "okay"  ;  
}  ;

 

 

But I believe that all of these elements lie lower down the DT include files eg in imx8qm-ss-dma.dtsi and imx8-ss-dma.dtsi...  

I still CANNOT receive ANYTHING on UART3 RX!

Believing that there may be a "pre-existing" conflict with something referring the removed second Ethernet socket I delved into both the uboot DT and also the uboot configuration settings. I first disabled fec2 in the uboot DT (and removed the pin assignments) but then went further and removed "CONFIG_FEC_MXC" from the uboot configuration.

Now when uboot starts I get the messages:

 

 

U - Boot SPL 2020.04  -  49374  - g575e54f56b - dirty ( Jun 27   2023   -   18  :  27  :  04   +  0100  )
Normal Boot
Trying to boot from MMC2_2
Load image from MMC / SD 0x76c00


U - Boot 2020.04  -  49374  - g575e54f56b - dirty ( Jun 27   2023   -   18  :  27  :  04   +  0100  )

CPU :     NXP i . MX8QM RevB A53 at 1200 MHz at 45C

Model : Variscite SPEAR - MX8
Boot :    SD1
DRAM :    8GiB_
MMC :     FSL_SDHC :   0  , FSL_SDHC :   1  
Loading Environment from MMC .  .  . Run CMD11 1  . 8V switch  
*  *  * Warning - No block device , using default environment

[  *  ]  - Video Link 0   (  800 x 480  )  
	[  0  ] dpu@ 56180000  , video
	  [  1  ] lvds - channel@ 0  , display
Run CMD11 1  . 8V switch  
Error : could not access storage .  
In :      serial
Out :     serial
Err :     serial

Part number : VSM - SP8 - 416  
Assembly : AS202199363
Production date :   2023 Mar 16  
Serial Number : f8 : dc : 7a : aa :  07  : d4
Run CMD11 1  . 8V switch  
Net :     No ethernet found .
Normal Boot
Hit any key to stop autoboot :    0   
Run CMD11 1  . 8V switch  
Run CMD11 1  . 8V switch  
6053543 bytes read in 82 ms (  70.4 MiB / s )  
Uncompressed size :   13070344   =   0xC77008  
Booting from mmc .  .  .  
102464 bytes read in 25 ms (  3.9 MiB / s )  
Loading hdp firmware from 0x000000009c000000offset0x0000000000002000
Loading hdp firmware Complete

 

 

... so it is finding NO ETHERNET port yet something is still preventing me from using UART3 RX to receive the GPS messages.

Can anyone please give me some advice on how to activate / enable lpuart3 on these pins so that it is functional or indeed if there is a potential conflict - what to remove?

All of my settings / code appear correct in-line with comparable reference eg in "imx8qm-mek.dts" (albeit that lpuart3 is status = "disabled"...)

Any suggestions?

Thank you very much in advance for any assistance!!!

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‎07-03-2023 10:33 PM
352 Views
Peter_ManyPebbles
Contributor II

Aldo,

Thank you very much for getting back to me quickly and for your assistance.

Following further investigation it unfortunately appears that the problems that we are experiencing are likely hardware related due to Variscite's system abstraction.

Although it does appear in the system log that lpuart3 is being correctly initialised, I don't believe that we are actually making a correct physical connection to it.

Thank you once again for getting back to me and we will investigate further with Variscite.

Kind regards,

Peter

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‎06-29-2023 11:55 AM
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AldoG
NXP TechSupport
NXP TechSupport

Hello,

The initial changes you made to LPUART3 should be enough to enable UART3 on the i.MX8QM, at least on our MEK board.

Could you share the schematic on how are you connecting to the UART3?
Could you share the boot log to see if the LPUART is being correctly enabled?
Have you tried a simple loopback test?

Also, since you are using both software and hardware from variscite I would suggest to contact their support channel as well.

Best regards,
Aldo.

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‎07-03-2023 10:33 PM
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Peter_ManyPebbles
Contributor II

Aldo,

Thank you very much for getting back to me quickly and for your assistance.

Following further investigation it unfortunately appears that the problems that we are experiencing are likely hardware related due to Variscite's system abstraction.

Although it does appear in the system log that lpuart3 is being correctly initialised, I don't believe that we are actually making a correct physical connection to it.

Thank you once again for getting back to me and we will investigate further with Variscite.

Kind regards,

Peter

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