TLPX, THS-PREPARE, THS-ZERO, THS-TRAIL, TWAKEUP Calculation

[alexreddy]

Hi,

Can anyone , say about the configuration of the following in i.MX6 MIPI DSI PHY

/* Clock lane timing control setting: TLPX, THS-PREPARE, THS-ZERO, THS-TRAIL, TWAKEUP */
0. TLPX
1. THS-PREPARE
2. THS-ZERO
3. THS-TRAIL
4. TWAKEUP                    

/* Data lane timing control setting: TLPX, THS-PREPARE, THS-ZERO, THS-TRAIL, TTA-GO, TTA-GET, TWAKEUP.*/

Could you please let me know the inputs?

[art]

All MIPI DSI PHY voltage and timing parameters are given in the corresponding Data Sheet document. For example, refer to the Section 4.11.12 of the i.MX6Dual/Quad Applications Processors for Consumer Products Data Sheet document, available on the processor's Documentation web page:

http://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-appli...

Have a great day,
Artur

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[lyu]

First, there is no section 4.11.12, I think you mean 4.12.12. 

I don't see answers for TTA-GO, TTA-GET timing control and configuration in above mentioned document. If I miss reading the document, could you please point me to the page of the document that has the info?