Registers for controlling integrated SOC power switch of i.MX7

[toshiharu_shimi]

Hello.
I would like to PowerDown i.MX7D processor.

According to  IMX7DRM.pdf, i,MX7D has integrated power switches for CPU and SOC on the chip as follows.
• SW_CPU0, Power switch for Arm Cortex-A7 CPU0.
• SW_CPU1, Power switch for Arm Cortex-A7 CPU1
• SW_SCU, Power switch for Arm Cortex-A7 Platform (SCU).
• SW_L2, Power switch for Arm Cortex-A7 L2 Cache memory.
• SW_SOC_PD, Power switch for the power down domain in VDD_SOC.
• SW_FUSE, Power switch for the eFuse programming power supply.
• SW_HSIC_1P0, Power switch for the USB HSIC PHY 1.0V power supply.
• SW_PHY_1P8, Power switch for PCIe and MIPI PHY 1.8V power supply.

"Both Arm and SOC has integrated power switches to shut off internal modules for power
saving in low power modes."

But I can't find Register.

Which Register can control these switch?

[weidong_sun]

Dear @toshiharu_shimi ,

On page 859 of iMX7D reference manual, you can find  5.4.5.6 Anadig Low Power Control Register (PMU_LOWPWR_CTRLn), 

On the following pages you will also find other registers, such as, 5.4.5.7 Anadig SNVS Miscellaneous Control Register (PMU_SNVS_MISC_CTRLn)

Power gated / ungated can be operated in above reqisters.

Check it, please!

Thanks!

Regards,

weidong